IC

Icarus Verilog

Icarus Verilog is an open-source Verilog hardware description language compiler and simulator supporting IEEE-1364 standards and portions of SystemVerilog. It generates netlists and simulation code, and is an alternative to proprietary tools.
Latest: 12.2022.06.11
Last checked: Apr 26, 2026 8:53am
Rank: 6544/15140
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Overview

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License: GNU General Public LicenseWinget: Available

Version & Lifecycle

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Current: 12.2022.06.11 Oldest supported: 0.2 Avg cadence: Regular updates (active development as of 2024)

Top Contributors

Top sitewide contributors:

  1. Anbarasan
  2. nico_k
  3. Bob
  4. Vigneshwaran

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Also known as

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verilogIcarus Verilog

Packaging Notes

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Available for Linux, FreeBSD, OpenSolaris, AIX, Microsoft Windows, and Mac OS X

Notes

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VHDL support was added but abandoned as of 2018. The project is primarily maintained by Stephen Williams.