Manos M. Tentzeris Bio

Email: [email protected]

Topics: Origins of Silicon Valley and the Electronics Packaging Society; the IEEE/SEMI/ASME Heterogeneous Integration Roadmap and how to use it (as editor for the 2019 Roadmap).

Past IEEE SF Bay Area Communications Director and Webmaster, and Life Fellow and Distinguished Lecturer of the IEEE

Paul Wesling received his BS in electrical engineering and his MS in materials science from Stanford University.  Following assignments at GTE/Lenkurt Electric, ISS/Sperry-Univac, Datapoint Peripheral Products (VP – Product Integrity), and Amdahl (mainframe testing), he joined Tandem Computers in Cupertino (now part of Hewlett Packard) in 1985.  He designed several multi-chip module prototypes, did thermal modeling and testing, managed Tandem’s Distinguished Lectures series, and organized a number of advanced technology courses for his Division and also for the IEEE.  He managed a grant from the National Science Foundation for the development of electronics packaging multimedia educational modules.  Paul retired from HP in 2001, and then served for 10 years as the Communications Director for the IEEE’s S.F. Bay Area Council and editor of the e-GRID, where he was known as “Mr. IEEE”.  He has observed the Silicon Valley for decades as an engineer, executive, resident, and educator.  He gives his IEEE DL lectures at universities, conferences and meetings around the world on the origins of Silicon Valley and its lessons for other tech hubs.

As vice president of publications from 1985 through 2008, he supervised four archival journals and a newsletter for IEEE’s Electronics Packaging Society (EPS).  He is a Fellow of the IEEE, and received the IEEE Centennial Medal, the Board’s Distinguished Service award, the Society Contribution Award, the IEEE’s Third Millennium Medal, and the Society President’s Recognition Award.  He has organized over 500 courses for the local IEEE chapter in the Santa Clara Valley (Silicon Valley), many of them held at Stanford University (and, more recently, at Silicon Valley company facilities).  An Eagle Scout, he served as scoutmaster of his local Boy Scout Troop for 15 years, was Advisor of a High-Adventure Crew, and enjoys backpacking, fly fishing, guitar and amateur radio (call sign: KM6LH). 

Manos M. Tentzeris Bio

Email: [email protected]

Topics: International developments in semiconductor packaging, manufacturing and assembly; SiP: Business and technology Trends; Drivers in advanced packaging; Flip chip and wafer level packaging 

E. Jan Vardaman is president and founder of TechSearch International, Inc., which has provided market research and technology trend analysis in semiconductor packaging since 1987.  She was the editor of Recent Developments in Tape Automated Bonding published by IEEE Press.  She is the co-author of How to Make IC Packages (by Nikkan Kogyo Shinbunsha), a columnist with Printed Circuit Design & Fab/Circuits Assembly, and the author of numerous publications on emerging trends in semiconductor packaging and assembly.  She served on the NSF-sponsored World Technology Evaluation Center (WTEC) study team involved in investigating electronics manufacturing in Asia and on the U.S. mission to study manufacturing in China.  She is a senior member of IEEE EPS and is an IEEE EPS Distinguished Lecturer.  She received the IMAPS GBC Partnership award in 2012, the Daniel C. Hughes, Jr. Memorial Award in 2018, the Sidney J. Stein International Award in 2019, and she is an IMAPS Fellow.  She is a member of MEPTEC, SMTA, and SEMI.  She serves on the JEDEC Task Force JESD-94 Working Group Application Specific Qualification Using Knowledge Based Test Methodology.  She has served on the IEEE CPMT Board of Governors for two terms.  Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium.  She received her M.A. from University of Texas, in 1981.     

Manos M. Tentzeris Bio

Email: [email protected]

Topics: RF/mmW/3D/electronics industry/nanotechnology/materials/packaging/3D printing/energy harvesting-zero power

Manos M. Tentzeris (S’89–M’92–SM’03–F’10) received the Diploma degree (magna cum laude) in electrical and computer engineering from the National Technical University of Athens, Athens, Greece, and the M.S. and Ph.D. degrees in electrical engineering and computer science from the University of Michigan, Ann Arbor, MI, USA.  

He is currently Ed and Pat Joy Chair Professor with the School of Electrical and Computer Engineering at Georgia Tech, where he heads ATHENA Research Group He has served as the Head of the GT ECE Electromagnetics Technical Interest Group, as the Georgia Electronic Design Center Associate Director of RFID/Sensors research, as the Georgia Institute of Technology NSF-Packaging Research Center Associate Director of RF Research, and as the RF Alliance Leader.  He has helped develop academic programs in 3-D/inkjet-printed RF electronics and modules, flexible electronics, origami and morphing electromagnetics, highly integrated/multilayer packaging for RF, millimeter-wave, sub-THz and wireless applications using ceramic and organic flexible materials, 5G/6G/sub-THz interconnects, packaging and modules, 4D RF electronics and phased arrays, paper-based RFID’s and sensors, wireless sensors and biosensors, wearable electronics, “Green” and transient electronics, energy harvesting and wireless power transfer, nanotechnology applications in RF, microwave MEMs, and SOP-integrated (UWB, multiband, mmW, and conformal) antennas. He has authored more than 850 papers in refereed journals and conference proceedings, 7 books, and 26 book chapters. He was a Visiting Professor with the Technical University of Munich, Munich, Germany, in 2002, with GTRI-Ireland, Athlone, Ireland, in 2009 and with LAAS-CNRS, Toulouse, France, in 2010 and a Humboldt Guest Professor with FAU, Nuremberg, Germany in 2019.  

Dr. Tentzeris was a recipient/co-recipient of many awards, including, the 2022 Georgia Tech Outstanding Doctoral Thesis Advisor Award, the 2021 IEEE Antennas and Propagation Symposium (APS) Best Student Paper Award, the 2019 Humboldt Research Prize, the 2017 Georgia Institute of Technology Outstanding Achievement in Research Program Development Award, the 2016 Bell Labs Award Competition 3rd Prize, the 2015 IET Microwaves, Antennas, and Propagation Premium Award, the 2014 Georgia Institute of Technology ECE Distinguished Faculty Achievement Award.

He is the Vice-Chair of the RF Technical Committee (TC16) of the IEEE CPMT Society. He is the Founder and Chair of the RFID Technical Committee (TC24) of the IEEE MTT-S and the Secretary/Treasurer of the IEEE C-RFID. He has served as an Associate Editor of the IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, the IEEE TRANSACTIONS ON ADVANCED PACKAGING, and the International Journal on Antennas and Propagation. He has given more than 150 invited talks to various universities and companies all over the world. He is a member of the URSI-Commission D and the MTT-15 Committee, an Associate Member of EuMA, a Fellow of the Electromagnetic Academy, and a member of the Technical Chamber of Greece. He is currently one IEEE EPS Distinguished Lecturer and he has served as one of the IEEE MTT-S Distinguished Microwave Lecturers and as one of the IEEE CRFID Distinguished Lecturers.

Andrew Tay Bio

Email: [email protected]

Topics: Thermomechanical reliability of microelectronics packages; Thermal and failure analysis of microelectronic devices; Thermal management of electronic and EV battery systems; Solder joint reliability; Delamination and fracture; Moisture effects; Modelling and simulation.

ANDREW TAY (M1991, SM2019, F2023) is currently a Visiting Scientist at the Singapore Hybrid-Integrated Next-Generation μ-Electronics Centre (SHINE), National University of Singapore (NUS). Prior to this he was a Senior Research Fellow at the Singapore University of Technology and Design and Professor in the Department of Mechanical Engineering, NUS. He obtained his B.E. (Hons I and University Medal) and PhD in Mechanical Engineering from the University of New South Wales, Australia. His research interests include thermo-mechanical reliability, thermal management of electronics and EV battery systems, reliability of solar photovoltaic modules and fracture mechanics. To date he has published more than 250 technical papers, 4 book chapters, 7 keynote presentations, 11 invited presentations and 3 panel discussions.

Dr Tay was the General Chair of the 1st Electronics Packaging Technology Conference (EPTC) in 1997. In 2006 he was appointed the inaugural Chairman of the EPTC Board, and is currently serving as its Chairman. He has been in the Executive Committee of the IEEE Singapore RS/EPS/EDS Chapter since 2000 and was its Chairman from 2010-2011 and 2018-2019. He has been involved in the international advisory boards and program committees of many electronics packaging conferences including DTIP, ECTC, EMAP, EPTC, EuroSimE, HDP, ICEPT, IEMT, IMPACT, InterPack, ITHERM and THERMINIC.

He was an Associate Editor of the ASME Journal of Electronic Packaging, an editorial board member of several journals including Microelectronics Journal and Finite Elements in Analysis and Design, and a guest editor of special issues of Microelectronics Reliability Journal, and Journal of Electronics Packaging. He is currently Co-Editor-in-Chief, Encyclopedia of Packaging Materials, Processes, and Mechanics.

He was a member of the EPS Education Committee from 1998 to 2007, and the coordinator of the Singapore Economic Development Board’s Specialized Manpower Program in Electronics Packaging and Wafer Fabrication in NUS. He has been awarded competitive research grants exceeding $14 Million for electronics packaging projects.

He was awarded the 2019 IEEE EPS David Feldman Outstanding Contribution Award, the 2012 IEEE EPS Exceptional Technical Achievement Award, the 2012 IEEE EPS Regional Contributions Award, the 2004 ASME Electronics & Photonics Packaging Division Engineering Mechanics Award, the 2000 IEEE Third Millennium Medal and the 2000 Special Presidential Recognition Award.

Ephraim Suhir Bio

Email: [email protected]

Topics: Accelerated life testing; Probabilistic physical design for reliability; Bonded assemblies; Thermal stress; Predictive modeling; Fiber optics structures: design for reliability; Dynamic response to shocks and vibrations 

Ephraim Suhir is on the faculty of the Portland State University, Portland, OR, USA, and Bordeaux Univ., France.  He is also CEO of a Small Business Innovative Research (SBIR) ERS Co. in Los Altos, CA, USA, is Foreign Full Member of the National Academy of Engineering, Ukraine (he was born in that country); Life Fellow of the Institute of Electrical and Electronics Engineers (IEEE), the American Society of Mechanical Engineers (ASME), the Society of Optical Engineers (SPIE), and the International Microelectronics and Packaging Society (IMAPS);  Fellow of the American Physical Society (APS), the Institute of Physics (IoP), UK, and the Society of Plastics Engineers (SPE); and Associate Fellow of the American Institute of Aeronautics and Astronautics (AIAA). Ephraim has authored  500+ publications, presented numerous plenary, keynote, invited and contributed talks and taught continued education courses worldwide. He received many professional awards, including 1996 Bell Labs. Distinguished Member of Technical Staff (DMTS) Award (for developing effective methods for predicting the reliability of complex structures used in AT&T and Lucent Technologies products), and 2004 ASME Worcester Read Warner Medal (for outstanding contributions to the permanent literature of engineering and laying the foundation of a new discipline “Structural Analysis of Electronic Systems”). He is the third “Russian American”, after S. Timoshenko and I. Sikorsky, who received this prestigious award. Ephraim’s most recent awards are 2023 SHEN International Research Award on Science, Health and Engineering” for the paper “Probabilistic Fitts’ Law and the Likelihod of the Tunguska Type of Event”,  Journal of Space Safety Engineering, 10(1), March 2023″;  2019 IEEE Electronic Packaging Society (EPS) Field award (for seminal contributions to mechanical reliability engineering and modeling of electronic and photonic packages and systems);  2019 IMAPS Lifetime Achievement award (for making exceptional, visible, and sustained impact on the microelectronics packaging industry and technology) and 2022 IEEE SCV Section Outstanding Engineer award (for seminal contributions to several critical IEEE fields, including probabilistic design-for-reliability of microelectronic and photonic materials, devices and systems, and the role of the human factor).

Rohit Sharma Bio

Email: [email protected]

Rohit Sharma¹, ², Senior Member, IEEE

¹ Department of Electrical Engineering, Indian Institute of Technology Ropar, Rupnagar, 140001, Punjab, India

² School of Electrical Engineering and Computer Science, The Pennsylvania State University, University Park, PA, 16802, USA

Topics:Design of High-speed Graphene-based and 2D materials-based nanoelectronics; Electrical-Thermal co-design of electronic packages and microsystems; Application of Machine Learning in design and analysis of interconnects; Heterogeneous integration.

Rohit Sharma (M’07 – SM’15) received the B.E. degree in electronics and telecommunication engineering from North Maharashtra University, India, in 2000, the M. Tech. degree in systems engineering from Dayalbagh Educational Institutes, India, in 2003 and the Ph.D. degree in electronics and communication engineering from Jaypee University of Information Technology, India, in 2009. He worked as a Post-Doctoral Fellow at the Design Automation Lab at Seoul National University, Seoul, Korea from Jan 2010 to Dec 2010. He was a Post-Doctoral Fellow at the Interconnect Focus Centre at Georgia Institute of Technology, Atlanta, USA from Jan 2011 to Jun 2012. 

Dr. Sharma is an Associate Professor (presently on leave) in the Department of Electrical Engineering at the Indian Institute of Technology Ropar and is currently a Research Professor at the School of EECS, Pennsylvania State University. His research interests include design of high-speed chip-chip and on-chip interconnects, Graphene based nano-interconnects, and signal and thermal integrity in high-speed interconnects. He is an Associate Editor of the IEEE Transactions on Components, Packaging and Manufacturing Technology and a program committee member in all major IEEE packaging conferences ECTC, EPEPS, SPI and EDAPS). In the past, he has been the chair of the IEEE EPS Technical Committee on Electrical Design, Modeling, and Simulation and is a Senior Member of the IEEE.

Dongkai Shangguan Bio

Email: [email protected]

Topics: Heterogeneous Integration and SiP; Electronics Packaging and Miniaturization; Materials; Thermal management; Reliability; Electronics manufacturing technology; Flexible hybrid electronics

Dr. Dongkai Shangguan, IEEE Fellow & IMAPS Fellow, is President of Thermal Engineering Associates Inc. (TEA), and a Strategic Advisor to innovative companies in the global semiconductor and electronics industry. Previously, he served as Corporate Vice President at Flex (formerly Flextronics) and as Chief Marketing Officer at STATSChipPAC (currently JCET). Early in his career, he held various technical and management responsibilities at Ford Electronics and Visteon.

Dr. Shangguan has published 3 books, authored/co-authored over 200 technical papers, and has been issued 32 U.S. patents.

Dr. Shangguan has served on the iNEMI Board of Directors, the IEEE EPS Board of Governors, and the IPC Board of Directors. He has received a number of recognitions for his contributions to the industry, including the Electronics Manufacturing Technology Award and the Outstanding Sustained Technical Contribution Award from IEEE EPS, the William D. Ashman Achievement Award from IMAPS, the President’s Award from IPC, and the Total Excellence in Electronics Manufacturing Award from the Society of Manufacturing Engineers.

Dr. Shangguan received his B.Sc. degree in Mechanical Engineering from Tsinghua University, China, MBA degree from San Jose State University, and Ph.D. in Materials from the University of Oxford, U.K. He conducted post-doctoral research at the University of Cambridge and The University of Alabama.

John Shalf Bio

Email: [email protected]

Topics: HPC System Integration, System Integration, Photonics and Packaging

John Shalf is the Department Head for Computer Science at Lawrence Berkeley National Laboratory.  He is also the 2024-2027 distinguished lecturer for the IEEE Electronics Packaging Society.   He also formerly served as the Deputy Director for Hardware Technology on the US Department of Energy (DOE)-led Exascale Computing Project (ECP) before he returned to his department head position at LBNL. He has co-authored over 100 peer-reviewed publications in parallel computing software and HPC technology, including the widely cited report “The Landscape of Parallel Computing Research: A View from Berkeley” (with David Patterson and others). In 2001 John won an R&D 100 award for the RAGE Remote Access Grid Explorer robot design.  Before coming to Berkeley Laboratory, John worked at the National Center for Supercomputing Applications and the Max Planck Institute for Gravitation Physics/Albert Einstein Institute (AEI), where he co-created the Cactus Computational Toolkit.  John is also an IEEE EPS Distinguished Lecturer from 2024-2027.

José E. Schutt-Ainé Bio

Email: [email protected]

Topics: Signal integrity, co-design for heterogeneous integration, computer-aided design tools for high-speed design, interconnects, microwaves and electromagnetics.

José E. Schutt-Ainé received the B.S. degree in electrical engineering from the Massachusetts Institute of Technology, Cambridge, in 1981, and the M.S. and Ph.D. degrees from the University of Illinois at Urbana-Champaign (UIUC), Urbana, in 1984 and 1988, respectively. He joined the Hewlett-Packard Technology Center, Santa Rosa, CA, as an Application Engineer, where he was involved in research on microwave transistors and high-frequency circuits. In 1988, he joined the Electrical and Computer Engineering Department at UIUC where he is currently involved in research on signal integrity for high-speed digital and high-frequency applications. Dr. Schutt-Ainé is an IEEE Fellow, EPS Distinguished Lecturer, and served as Co-Editor-in-Chief of the IEEE Transactions on Components, Packaging and Manufacturing Technology (T-CPMT) from 2007 to 2018. He is currently serving as a member of the Board of Governors for the IEEE Electronics Packaging Society.

Katsuyuki Sakuma DL Bio

E-mail: [email protected]

Topics: 3D integration technologies, bonding technologies, advanced packaging, and biomedical sensors

Katsuyuki Sakuma is a Principal Research Staff Member, a Research Manager, and an IBM Master Inventor at the IBM Thomas J. Watson Research Center in New York. He is also a Visiting Professor at the Department of Biomedical Engineering, Tohoku University, Japan and was a visiting professor at National Chiao Tung University, Taiwan. He has over 20 years of experience of researching 3D chip integration technologies and performing various semiconductor packaging research and development projects. His current research interests include 3D integration technologies, bonding technologies, advanced packaging, and biomedical sensors.

He has published more than 110 peer-reviewed journal papers and conference proceeding papers, including five book chapters in the semiconductor and electronic packaging area. He also holds over 100 issued or pending U.S. and international patents. He has been recognized with the IBM 20th Invention Achievement Award in 2022 and an Outstanding Technical Achievement Award (OTAA) in 2015 for his contribution and leadership in the area of 3D chip integration technology development. He was also given the 2018 Exceptional Technical Achievement Award from IEEE Electronics Packaging Society and the 2017 Alumni Achievement Award from his Alma Mater, the School of Engineering at Tohoku University, for his contribution to 3D chip stack technology development in the electronics packaging industry. He was co-recipient of the IEEE CPMT Japan Society Best Presentation Award in 2012, and the IMAPS “Best of Track” Outstanding Paper Award in 2015.

Dr. Sakuma received his B.E. and M.E. degrees from Tohoku University, and the Ph.D. degree from Waseda University, Japan. He is currently serving as an Associate Editor for IEEE Transactions on Components, Packaging and Manufacturing Technology (CPMT). He served as an Associate Editor of the Institute of Electronics, Information and Communication Engineers (IEICE, Japan) from 2003 until 2005. He has served as a committee member of the IEEE ECTC Interconnections sub-committee since 2012, for the IEEE International Conference on 3D System Integration (IEEE 3DIC) since 2016, and for the IEEE International Reliability Physics Symposium (IEEE IRPS) from 2017 to 2019. He has been a senior member of IEEE since 2012.

Gamal Refai-Ahmed Bio

Email : [email protected]

Topics: Thermo-mechanical Semiconductor and Electronics Industry Roadmap and directions, Advanced holistic Thermo-mechanical  solution, assembly and reliability of  Heterogeneous Packaging  and Silicon Photonics, Future thermo-mechanical technology, architecture for component and system

Dr. Gamal Refai-Ahmed, Life Fellow ASME, Fellow IEEE, Member of National Academy of Engineering, Fellow Canadian Academy of Engineering, Fellow Engineering Institute of Canada, is AMD Sr Fellow.  He obtained the Ph. D. degree from the University of Waterloo. 

He has been recognized as one of the global technical leaders through his numerous publications (more than 120 publications) and patents& patents pending US and International (more than 110). His contributions are clearly seen in several generations of both GPU, CPU and FPGA for HPC, AI, ML, NIC, Game Console, Aerospace& Defense and Telecom products.  

In 2015-2021, Gamal was a Fellow Engineer in Xilinx. This is to initiate the heterogeneous integration of system level power, thermal, mech and assembly with package and Si development in first initial planning.  He has been a key player to introduce all Xilinx Alveo products and high-end Si  CoWos, InFo, Chiplets  PKG  to Xilinx Customers. He was behind the introduction of the first Lidless FPGA   20, 16, 7nm technology nodes with highest warpage in mass production in Xilinx Alveo products, and its Telecom, AI, HPC customers (e.g. MSFT, AWS, Nokia, Cisco and A&D).  his developed strategy of technology enable Xilinx FPGA  products to outperform the Intel/Altera Products.  As a result, he was promoted in Mid of 2020 to Xilinx Fellow.

Gamal is the recipient of 2008 excellent thermal management award, 2010 Calvin Lecture and 2013 K16- Clock award in recognition for his scientific contributions and leadership of promoting best electronics packaging engineering practice. In 2014, Gamal received the IEEE Canada R. H. Tanner Industry Leadership for sustained leadership in product development and industrial innovation. In 2016, ASME awarded Gamal the ASME Service Award. State University of New York, Binghamton University awarded him the Innovation Partner Award for his industrial role with Binghamton University. In continuation to Dr Refai contributions to the best engineering practice, State University of New York at Binghamton awarded him the Presidential University medal in 2019 which is the highest recognition honor by the university.  In 2021, Gamal was elected to IEEE Fellow and  EIC Fellow. Gamal was elected as a member in the National Academy of Engineering in 2024. 

Dr. Gamal Refai-Ahmed, a Life Fellow of the American Society of Mechanical Engineers (ASME), Fellow of the Institute of Electrical and Electronics Engineers (IEEE),  Fellow of the Canadian Academy of Engineering, Fellow of the Engineering Institute of Canada and a Member of the National Academy of Engineering (NAE), has led a prolific career spanning over three decades in both industry and academia. Renowned for his pioneering efforts in thermal management, system integration, and advanced packaging, his work has been instrumental in driving innovation and leadership in the engineering domain.

Technical Pioneering: Authored more than 125 publications and holds over 115 US and international patents, influencing advancements across a broad spectrum of fields such as High-Performance Computing (HPC), Artificial Intelligence (AI), Machine Learning (ML), Network Interface Cards (NICs), gaming consoles, aerospace and defense, and telecommunications.

At AMD, he was pivotal in integrating system-level considerations—power, thermal, mechanical, and assembly—within package and silicon development, leading to the launch of high-end silicon GPU and FPGA  packages.

Leadership and Recognition: Dr. Refai-Ahmed’s contributions have been acknowledged through prestigious awards, including the ASME Service Award (2016), IEEE Canada R. H. Tanner Industry Leadership Award (2014), and the SUNY Binghamton University Presidential Medal (2019).

His election as a Fellow of ASME, IEEE, EIC, and CAE, and his induction into the NAE, underscore his exceptional impact on the engineering community.

Dr. Refai-Ahmed’s unwavering dedication to advancing engineering boundaries and promoting excellence has solidified his position as a pivotal asset to the NAE. His remarkable career not only inspires future generations of engineers but also stands as a testament to the transformative power of innovation and leadership in engineering. 

Dr. Gamal Refai-Ahmed’s  technical interest in thermal management, system integration, and advanced packaging, brings over three decades of impactful innovation across HPC, AI, ML, NICs, and more. His pioneering work at AMD integrating system-level considerations, yielded high-end Si packages and groundbreaking lipless FPGAs, boosting AMDx’s market position. Driven by a passion for pushing boundaries and fostering excellence, he has authored over 120 publications and secured 110+ patents, showcasing his dedication to impactful engineering. This makes him a valuable asset to the NAE and an inspiration to future generations.

Mark Poliks DL Bio

Email: [email protected]

Topics: Materials and Processes, Advanced Manufacturing, Flexible Hybrid Electronics, High Speed and Additive

MARK POLIKS (M: 2004) is Empire Innovation Professor of Engineering, Professor of Systems Science and Industrial Engineering, Professor of Materials Science and Engineering and Director of the Center for Advanced Microelectronics Manufacturing (CAMM) at the State University of New York at Binghamton.  In 2006 he established the first research center (CAMM), to explore the application of roll-to-roll processing methods to flexible electronics and displays, with equipment funding from the United States Display Consortium (USDC) and the Army Research Lab.  His research is in the areas of industry relevant topics that include: high performance electronics packaging, flexible hybrid electronics, medical and industrial sensors, materials, processing, aerosol jet printing, roll-to-roll manufacturing, in-line quality control and reliability.  He has received more than $20M in research funding from Federal, New York State and corporate sources and more than $30M in equipment funding from federal and state sources.  He is the recipient of the SUNY Chancellor’s Award for Excellence in Research.  He leads the New York State Node of the DoD NextFlex Manufacturing USA and was named a 2017 NextFlex Fellow.  He has authored more than one-hundred technical papers and holds forty-six US patents.  Previously he held senior technical management positions at IBM Microelectronics and Endicott Interconnect.  Poliks is a member of technical councils for the FlexTech Alliance, NBMC and NextFlex, and on the NextFlex Governing Council.  He is an active member of the IEEE Electronics Packaging Society Electronic Component and Technology Conference and served and the 69th ECTC General Chair.   Poliks received dual undergraduate degrees, with honors, in chemistry and mathematics from the University of Massachusetts and a Ph.D. from the University of Connecticut in materials science and engineering.  He was a McDonnell-Douglas post-doctoral fellow working on solid-state magnetic resonance at Washington University, St. Louis before starting his career at IBM.

Eric Perfecto DL Bio

Email: [email protected] 

Topics:Fine pitch interconnect, chip to chip and chip to laminate connection, UBM and solder selection, chip package interaction and 2.5D fabrication

ERIC PERFECTO (M’95, SM’01, F’17) has extensive experience working in microelectronics. At IBM, Eric has led the development of multi-level Cu-polyimide advanced packages for high-end systems, followed by the introduction of Pb-free solder interconnects and 2.5D wafer finishing. As part of the IBM Microelectronics Division divestiture, Eric moved to GLOBALFOUNDRIES where he established a Si Photonics packaging development line. In 2019 he returned to IBM part time to establish a heterogeneous integration line in Albany. He holds a M.S. in Chemical Engineering from the University of Illinois and a M.S. in Operations Research from Union College.

An author of more than 80 technical papers and three book chapters, Eric received two Best Conference Paper Awards (2006 ESTC and 2008 ICEPT-HDP) and the 1994 Prize Paper Award from CPMT Trans. on Adv. Packaging. He holds 55 US patents and has been honored with two IBM Outstanding Technical Achievement Awards.

Eric served as the 57th ECTC General Chair, the 55th ECTC Program Chair and is the current ECTC Publicity chair. For the last 12 years, Eric’s popular Flip Chip Fabrication and Interconnection course has been given at ECTC to great reviews. He is an EPS Distinguish Lecturer, an IEEE Fellow, and has achieved IMAPS and SPE senior membership. 

Eric has represented the EPS members previously, elected 4 times to the BoG. For 3 years he served as the EPS Strategic Director of Global Chapters and Membership where he focused on enhancing the EPS membership value.  Through his efforts, the CPMT Transactions are now part of the EPS membership. For 8 years, he was the EPS Awards Program Director responsible for the EPS Mayor Awards, the Regional Awards, the PhD Fellowship, the ECTC Student Travel Awards and the ECTC Volunteer Award.  Currently, he chairs the EPS Field Award committee. At a local level, Eric is the membership Chair of the Mid-Hudson IEEE Section and founding member of the EPS Mid-Hudson EPS Chapter where he serves as membership chair.

Katherine “Kitty” Pearsall DL Bio

Email: [email protected]

Topics: Supply chain, component qualification and end quality; Leadership

KITTY PEARSALL (AM’84-M’01-SM’02) received the BS degree in Metallurgical Engineering (1971) from the UT El Paso. Kitty received the MS and Ph.D. degree in Mechanical Engineering and Materials from the UT Austin in 1979 and 1983 respectively. Kitty worked for IBM from 1972 to 2013. In 2005 Kitty was appointed an IBM Distinguished Engineer and was elected to the IBM Academy of Technology. Kitty was a process consultant and subject matter expert working on strategic initiatives impacting component qualification and end quality of procured commodities. She engaged with worldwide teams implementing cross-brand, cross commodity processes/products that delivered high quality/high reliability end product.

Kitty received 4 IBM Outstanding Technical Achievement Awards; holds 9 US patents; 2 patents pending; and 8 published disclosures. She has numerous internal publications as well as 22 external publications in her field. Kitty is a licensed Professional Engineer (Texas since 1993). Kitty was the recipient of the UT Austin – Cockrell Engineering Distinguished Engineering Graduate Award in 2007 followed by induction into the UT Mechanical Engineering Dept. Academy of Distinguished Alumni in 2008. Kitty was awarded the Women in Technology Fran E. Allan Mentoring Award (2006) in recognition of her people development both in and outside of IBM. Currently Kitty is President of Boss Precision Inc. and works as an Independent consultant. This has included a one year engagement with Shainin Corporation.

Kitty is an active member in IEEE and CPMT. She is a member of TMS, American Society of Metals, and WIE. Kitty has more than 22 years’ experience with ECTC serving as a member of the ECTC Manufacturing Technology Committee (1993-2013) and as the Professional Development Course Chair since 2006. During Kitty’s 10 years on the CPMT Board of Governors she has served in many roles: Member at Large, Strategic Awards Director, VP of Education and currently Director of Chapter Programs. In each role Kitty made key contributions.

Kitty introduced the Regional Contribution Awards. She established the baseline for the CPMT Distinguished Lecturer’s (DLs) Program. The history of the DLs presentations to Universities, Research Centers, Conferences and CPMT Chapters was charted to determine if the program was meeting its founding principal; i.e., primarily supporting the CPMT chapters. Review of the data noted that this was not the case. Therefore Kitty focused on increasing Chapter usage which did improve over time. DL Budget tracking of planned versus actuals was initiated. Lastly, Kitty documented the roles and responsibilities of the VP Education and passed these on to the new VP. As Director of Chapter Programs Kitty is focusing on worldwide Chapter Communication as well as ensuring Chapters know their benefits and how to access them. First deliverable was a Worldwide Chapter Communication Survey highlighting best practices amongst them.

Rajen Murugan Bio

Email: [email protected]

Topics: Multiphysics and System Co-Design modeling for complex analog and mixed-signal packaging, mmWave/THz packaging signal integrity, advanced power electronics packaging/module, and system-Level EMI/EMC modeling, analysis, and characterization.

Dr. Rajen Murugan specializes in developing multiphysics system co-design simulation and modeling methodologies for advanced IC packaging and systems. He is currently a Distinguished Member of the Technical Staff (DMTS) with Texas Instruments, Inc. He has 46 granted patents and 98 under review at the USPTO. He has published over 75 papers in peer-reviewed IEEE journals and conferences. Dr. Murugan holds a Ph.D. in Applied Electromagnetics from the University of Manitoba, Canada. He is an Affiliate Assistant Professor with the University of Washington Electrical Engineering Department, a Distinguished Lecturer for the IEEE Electronics Packaging Society (EPS), an Associate Editor for the IEEE Transactions on CPMT journal, an IEEE Fellow, the founder of the IEEE EPS Dallas Chapter, and the current Chair of the IEEE Dallas Section (Region 5).

James Morris Bio

Email: [email protected]

Topics: Electrically conductive adhesives; Electronics packaging; Nanotechnologies

Jim Morris is an ECE Professor Emeritus at Portland State University, Oregon, and an IEEE Life Fellow. He founded the Institute for Electronics Packaging Research (which became the Integrated Electronics Engineering Center) at SUNY-Binghamton and served as EE/ECE Department Chair there and at Portland State.  He has B.Sc. (1965) and M.Sc.(hons) degrees (1967) in Physics from the University of Auckland, NZ, and a Ph.D. in EE from the University of Saskatchewan, Canada, and was awarded a Doctor Honoris Causa degree by Bucharest Polytechnic University in 2015. Jim has served the IEEE Electronics Packaging Society (EPS,) including when it was CPMT, as Treasurer (1991-1997,) BoG member (1996-1998), VP for Conferences (1998-2003,) Distinguished Lecturer (2000- ,) CPMT-Transactions Associate-Editor (1998- ,) the EPS IEEE Nanotechnology Council (NTC) representative (2007-2012,) etc., and won the 2005 CPMT David Feldman Outstanding Contribution Award. He was General Conference Chair of Adhesives in Electronics (1998,) Advanced Packaging Materials (2001,) and Polytronic (2004,) along with other conference organizing roles, e.g., ECTC Program Committees and the ISSE Steering Committee (2001-2024.) He has co-authored one book on electronics packaging reliability and edited five more, including two (2008, 2018) on nanopackaging, and co-edited two on nanoelectronics. He served as the NTC Awards Chair (2008-2012,) Conferences VP (2013-204,) Finance VP (2015-2018,) President-Elect (2019,) President (2020-2021,) Past-President (2022-2023,) and the Fellows Search Committee Chair (2024- .) He established the Nanotechnology Council Nanopackaging TC, which also functions as the EPS Nanotechnology TC, contributes to IEEE Nanotechnology Magazine, chaired NANO 2011 and 2020, and NMDC 2018, and was Program Chair for NMDC 2023. His research interests have ranged from isotropic conductive adhesives, nanopackaging, nanoelectronics simulation, and discontinuous thin metal films to automotive engine control.  He is actively involved in international engineering education and NTC chapter development. Locally, he founded or co-founded the Oregon Chapters of the IEEE Education Society, EPS and NTC. He has had numerous international visiting appointments, most notably with Nokia-Fulbright (Finland,) Erskine (N.Z.) and Royal Academy of Engineering (U.K.) Fellowships. Jim has taught continuously for 59 years, mainly online to China most recently, and published 63 journal papers, 107 refereed conference papers, 33 book chapters, and one patent, plus ~80 other conference presentations.

Ravi Mahajan DL Bio

Email: [email protected]

Topics: Advanced Packaging Architectures, Assembly Processes and Thermal Management 

RAVI MAHAJAN is an Intel Fellow responsible for exploring and developing innovative technologies for assembling and packaging semiconductor components, with a particular emphasis on future generations of semiconductor manufacturing technology. Ravi also represents Intel in academia through research advisory boards, conference leadership and participation in various student initiatives. For over three decades he has led efforts to define and set strategic direction for package architecture, technologies, and assembly processes for multiple iterations of Intel packaging and assembly architectures and processes. Dr. Mahajan joined Intel in 1992 after earning Ph.D. in Mechanical Engineering from Lehigh University.

A prolific inventor and recognized expert in microelectronics packaging technologies, Mahajan is an inventor on 151 patent families, and these 151 patent families have led a total of 450 patents and applications. This includes the original patent for a silicon bridge that became the foundation for Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) technology currently deployed in high volume manufacturing for semiconductor devices and graphics parts. His early insights also led to high-performance, cost-effective cooling solutions for high-end microprocessors and the proliferation of photo-mechanics techniques used for thermo-mechanical stress model validation. Ravi has written several book chapters and more than 50 papers on topics related to his area of expertise.  He has delivered numerous plenary addresses and invited talks all over the world.  He is also one of the leaders of the IEEE-SEMI-ASME driven Heterogeneous Integration Roadmap (HIR) effort that today underpins R&D efforts in packaging across multiple geographies.

His contributions during his Intel career have earned him numerous industry honors, including the SRC’s 2015 Mahboob Khan Outstanding Industry Liaison Award, the 2016 THERMI Award from SEMITHERM, the 2016 Allan Kraus Thermal Management Medal & the 2018 InterPACK Achievement award from ASME, the 2019 “Outstanding Service and Leadership to the IEEE” Awards from IEEE Phoenix Section & Region 6 and more recently the 2020 Richard Chu ITherm Award and the 2020 ASME EPPD Excellence in Mechanics Award. He is one of the founding editors for the Intel Assembly and Test Technology Journal (IATTJ) and currently VP of Publications & Managing Editor-in-Chief of the IEEE Transactions of the CPMT. He has long been associated with ASME’s InterPACK conference and was Conference Co-Chair of the 2017 Conference. Ravi is a Fellow of two leading societies, ASME and IEEE.  He was elected to the National Academy of Engineering in 2022 for contributions to advanced microelectronics packaging architectures and their thermal management.

John H. Lau Bio

Email: [email protected]

Topics: Electronics and Photonics 2D and 3D packaging and manufacturing

John H. Lau (Life Fellow, IEEE) received the Ph.D. degree from the University of Illinois at Urbana–Champaign in 1977 and three master degrees from the University of British Columbia in 1973, the University of Wisconsin–Madison in 1974, and Fairleigh Dickinson University in 1979. He also earned a bachelor’s degree from the National Taiwan University in 1970. He was a Senior Scientist/MTS with the Hewlett-Packard Laboratory and Agilent, Palo Alto, CA, USA, for 20 years, the Director of the System Packaging Laboratory, Institute of Microelectronics, Singapore, for two years, a Visiting Professor with The Hong Kong University of Science and Technology, Hong Kong, for one year, a Specialist with the Industrial Technology Research Institute, Taiwan, for five years, and a Senior Technical Advisor with ASM Pacific Technology, Hong Kong, for five years. He was the CTO from July 2019 to June 2021 and has been a Senior Special Project Assistant with Unimicron Technology Corporation, Taiwan, since July 2021. He has more than 40 years of research and development and manufacturing experiences in semiconductor packaging and surface-mount technology assembly, published more than 528 peer-reviewed papers (380 are the principal investigator), 53 issued and pending U.S. patents (34 are the principal inventor), and 23 textbooks such as Chiplet Design and Heterogeneous Integration Packaging (Springer, 2023) and Flip Chip, Hybrid Bonding, Fan-in and Fan-out Technology (Springer, 2024). John is an elected ASME Fellow and IMAPS Fellow and has been actively participating in industry/academy/society meetings/conferences to contribute, learn, and share. He received many awards, including the ASME Worcester Reed Warner Medal and the IEEE Components Packaging and Manufacturing Technology Field Award.

The technical topics I can cover are:

• Chipet Design and Heterogeneous Integration Packaging

• Co-Packaged Optics – Heterogeneous Integration of Photonic IC and Electronic IC

• Advanced Packaging: 2D, 2.1D, 2.3D, 2.5D, and 3D IC Integration

• Organic Interposers vs. TSV Interposers

• Packaging Technologies Driven by Artificial Intelligence

• Flip Chip and Hybrid Bonding Technology

Pradeep Lall DL Bio

Email: [email protected]

Topics: Semiconductor Packaging, Modeling and Simulation, Reliability in Harsh Environments, Shock/Drop/Vibration, Cu Wirebonding, Flexible Hybrid Electronics, Additive Manufacturing, Prognostics and Health Management, LEDs, Micro CT Measurements 

PRADEEP LALL (M:1990, SM: 2008, F: 2012) is the MacFarlane Endowed Professor in the Department of Mechanical Engineering and the Director of NSF Center for Advanced Vehicle and Extreme Environment Electronics at Auburn University.  He serves on the Technical Council and Governing Council of NextFlex Manufacturing Institute.  Dr. Lall is author and co-author of 2-books, 14 book chapters, and over 500 journal and conference papers in the field of electronics reliability, safety, energy efficiency, and survivability.  Dr. Lall, a fellow of IEEE, fellow of the ASME, and fellow of the Alabama Academy of Sciences.  Dr. Lall is recipient of the NSF’s Alex Schwarzkopf Award for Technology Innovation, Alabama Academy of Science Wright A, Gardner Award, IEEE Exceptional Technical Achievement Award, ASME-EPPD Applied Mechanics Award, SMTA’s Member of Technical Distinction Award, Auburn University’s Creative Research and Scholarship Award, SEC Faculty Achievement Award, Samuel Ginn College of Engineering Senior Faculty Research Award, Three-Motorola Outstanding Innovation Awards, Five-Motorola Engineering Awards, and Twenty Best-Paper Awards at national and international conferences.  Dr. Lall has served in several distinguished roles at national and international level including serving as member of National Academies Committee on Electronic Vehicle Controls, Member of the IEEE Reliability Society AdCom, IEEE Reliability Society Representative on the IEEE-USA Government Relations Council for R&D Policy, Chair of Congress Steering Committee for the ASME Congress, Member of the technical committee of the European Simulation Conference EuroSIME, and Associate Editor for the IEEE Transactions on Components and Packaging Technologies.  He received the M.S. and Ph.D. degrees in Mechanical Engineering from the University of Maryland and the M.B.A. from the Kellogg School of Management at Northwestern University.

Beth Keser DL Bio

Email: [email protected]

Topics: Fan-Out Wafer Level Packaging and Wafer Level Packaging structures; processes, materials, tools, design rules and roadmaps; Advanced Packaging; Introduction to Packaging; and photoimageable liquid polymer films.

BETH KESER, Ph.D. is a recognized global leader in the semiconductor packaging industry with over 26 years of experience. Beth’s excellence in developing revolutionary electronic packages for semiconductor devices has resulted in 42 US patents and patents pending and over 50 publications in the semiconductor industry.

For over 7 years, Beth led the Fan-Out and Fan-In Wafer Level Packaging Technology Development and NPI Group at Qualcomm where she and her team qualified over 50 products resulting in over 10 billion units shipped–technology consumers around the world enjoy in mobile phones. Following that, Beth led Intel’s worldwide Packaging & Systems Technology department for 7 years. Beth is currently VP of Manufacturing Technology at Zero ASIC.  Beth is also an IEEE Fellow and IEEE EPS Distinguished Lecturer who chaired IEEE EPS’s 2015 ECTC. Based in San Diego, Beth was the President of the International Microelectronics Assembly and Packaging Society (IMAPS) from 2021-2023 and is currently Past President.

Beth has published two edited volumes: “Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Applications Spaces” (Wiley, 2021) and “Advances in Embedded and Fan-Out Wafer Level Packaging Technologies” (Wiley, 2019). In 2021, Beth received the IEEE EPS Exceptional Technical Achievement Award for contributions in the field of Fan-Out Wafer Level Packaging. Finally, Beth has lectured at Georgia Tech, UCLA, Purdue, Hong Kong University of Science and Technology, Florida International University, and Portland State and given keynotes and participated in panels at prominent electronic packaging and semiconductor conferences worldwide. Currently, Beth teaches professional development courses at IMAPS conferences and online at IMAPS Academy (imaps.org).

Bio Iyer

SUBRAMANIAN (SUBU) S. IYER (S’76-M’81-SM’88-F’95) is Distinguished Chancellor’s Professor and holds the Charles Reames Endowed Chair in the Electrical Engineering Department at the University of California at Los Angeles and Director of the Center for Heterogeneous Integration and Performance Scaling (CHIPS). He obtained his B.Tech. from IIT-Bombay, and Ph.D. from UCLA and joined the IBM T.J. Watson Research Center at Yorktown heights, NY and later moved to the IBM systems and Technology Group at Hopewell Junction, NY where he was appointed IBM Fellow and was till recently Director of the Systems Scaling Technology Department. His key technical contributions have been the development of the world’s first SiGe base HBT, Salicide, electrical Fuses, embedded DRAM and 45nm technology used at IBM and IBM’s development partners to make the first generation smartphone devices and more recently developing commercial 3D die stacking processes used in the Hybrid Memory Cube and Silicon Interposer products. He also was among the first to commercialize bonded SOI for CMOS applications through a start-up called SiBond LLC. He has published over 300 papers and holds over 70 patents. At UCLA he is pioneering the development of new ways for heterogeneous integration. His current technical interests and work lie in the area of advanced packaging and three-dimensional integration for system-level scaling and new integration and computing paradigms as well as the long-term semiconductor and packaging roadmap for logic, memory and other devices including hardware security and supply-chain integrity. He has received several outstanding technical achievements and corporate awards at IBM. He is an IEEE Fellow and a Distinguished Lecturer of the IEEE EDS. He is a Distinguished Alumnus of IIT Bombay and received the IEEE Daniel Noble Medal for emerging technologies in 2012. He also studies Sanskrit in his spare time.

He served as secretary of the IEEE student Chapter at IIT Bombay (‘75-‘76). He has served two terms on the EDS BoG (2009-2015) and currently is EDS Treasurer. He has served as the Chairman of the IEEE Mid-Hudson EDS chapter (2007-2008). He serves as a non-voting member of the CPMT BoG and is the EDS-CPMT liaison volunteer. He also serves on an ad-hoc committee on rebranding the CPMT and serves on the steering committee of the Heterogeneous Integration Roadmap committee sponsored by CPMT and other societies and SEMI. He mentors at the local IEEE student chapters. He has served on the Fellows’ committee for EDS and IEEE. He is also a member of the APS.

Madhu Iyengar DL Bio

Email: [email protected]

Topics:  Thermal Management, Heat Transfer, Liquid Cooling, Heterogeneous Integration of Packages, Data Center Architecture and Energy Efficiency, ML System Physical Architecture

Madhu Iyengar is a Principal Engineer at Google and a lead in innovative product development and path-finding for IT hardware and physical infrastructure, including chip packages, server systems, and data centers.  Madhu is also a Technical Lead Manager with technical and managerial responsibilities, and with a mission to develop and deliver excellent thermal systems, products, and advanced technologies, with a focus on end-to-end, chip-to-chiller, infrastructure stack optimization and innovation opportunities, in collaboration with cross-functional partners. Prior to working at Google, Madhu was a Hardware Architect/Engineer at Facebook, and a Senior Engineer at IBM. He has co-authored over 115 technical papers in journals and conference proceedings and two edited books, holds more than 300 US Patents, is an elected Fellow of the American Society of Mechanical Engineers (ASME), and a Member of IEEE and ASHRAE.

Madhu has served as an Associate Editor for the IEEE Electronics Packaging Society CPMT Transactions, for the ASME Journal of Electronic Packaging, and for the ElectronicsCooling Magazine, respectively. He has also served as a voting member of the ASHRAE TC9.9 Mission Critical (Data Center) Facilities committee, and as the General Chair of the 2016 IEEE ITherm Conference.  He is currently Chair for Thermal Technical Working Group for IEEE Electronics Packaging Society Roadmap on Heterogeneous Integration. Madhu has a PhD in Mechanical Engineering from the University of Minnesota, and a BE in Mechanical Engineering from the University of Pune, India.

Deepak Goyal DL Bio

email: [email protected]

Topics: 2.5D/3D packaging technologies, Failure mechanisms, Failure analysis methods and challenges.

Deepak Goyal

• Manager of Analytical chemistry labs in support of the microelectronic package/substrate development and manufacturing.
• Book co-Editor: 3D Microelectronic Packaging: From Fundamentals to Applications and 3 Book chapters
• Associate Editor for IEEE Transactions on Advance Packaging (2008 – Present), and Guest Editor  for IEEE Microelectronics Reliability journal (2011) and IEEE CPMT Journal of  Advanced packaging (2018)
• Editor for iATTJ  (Intel internal Journal) (1998-2006)
• Professional Development courses on Package FA/FI and failure mechanisms at the ECTC (2003-2017)
• Active in tech. Committee or session at ECTC, Interpack (ASME). IRPS (IEEE), ISTFA (ASME)
• Over 60 Technical publications in the industry recognized Journals and Conferences and >50 Intel internal publications
• 2 Intel Achievement Awards and >30 Intel Divisional Recognition Awards
• 13 Issued patents
• ·IEEE Fellow

Xuejun Fan Bio

Email: [email protected]

Topics: Design, modeling and reliability in micro-/nano- electronic packaging and microsystems

Xuejun Fan is a Regents’ Professor of Texas State University System, and a Mary Ann and Lawrence E. Faust Endowed Professor at Lamar University, Beaumont, Texas. Dr. Fan received a B.S. degree in Applied Mechanics and an M.S. degree in Solid Mechanics from Tianjin University in 1984 and 1986, respectively. In 1989 he earned a Ph.D. degree in Solid Mechanics from Tsinghua University.

Dr. Fan is an IEEE Fellow, and an IEEE Distinguished Lecturer. He received the Outstanding Sustained Technical Contribution Award in 2017, and the Exceptional Technical Achievement Award in 2011 from Electronic Packaging Society of IEEE. He is a co-chair of Modeling and Simulation in Heterogeneous Integration Roadmap committee.

Dr. Fan gained 10-year significant experience in semiconductor industry with the Institute of Microelectronics (IME) in Singapore (1997-2000), Philips Research in Briarcliff Manor (2000-2003), and Intel in Chandler, Arizona (2004 – 2007), prior to Lamar University.

Dr. Fan’s current area of interest is multi-scale, multi-physics modeling, characterization, and reliability study for heterogeneous integration. He has published 4 books, 25 book chapters, and over 300 technical papers.

In his early academia career in China, Dr. Fan was the recipient of a Young Faculty Award from the Fok Ying-Tung Education Foundation in 1994. He received the nominee for the title of “Ten Outstanding Youth of China” in 1991.

Kuan Yew Cheong Bio

Email:[email protected] 

Topics: Engineering Materials for Advanced Packaging and Physical Failure Analysis and Strategy

KUAN YEW CHEONG (S’01–M’05-SM’15) is a Professor of School of Materials & Mineral Resources Engineering at the Universiti Sains Malaysia, Malaysia. He received his PhD from Griffith University, Australia in 2004. Currently, he is working on designing, processing, characterizing of engineering materials for wafer (Si- and wide bandgap-based semiconductors) and package level, including physical failure analysis of these applications. He has published more than 250 high impact-factor journals, 6 reputable book chapters, 5 edited books, 1 granted Malaysian Patent, and delivered close to 300 technical training courses, for the past 14 years, related to failure analysis techniques/strategies and engineering materials for wafer and advanced packaging. Prof. Cheong is also actively involved in IEEE EPS activities, serving as a Vice President of IEEE EPS Malaysia Section and Executive Committee for more than 10 years, organizing committees of IEEE EPS/IEEE flagship conferences, such as IEMT, and delivered tutorials and keynotes in conferences organized by IEEE.  Currently, he is Editor-in-Chief of “Materials Science in Semiconductor Processing” (Elsevier), Fellow of The Institution of Engineers Malaysia (IEM), Senior Member of IEEE, Principal Interviewer for Professional Interview of IEM, Senior Evaluation Panel of Engineering Program Accreditation under Engineering Accreditation Council, Malaysia, Founding Chairman of Material Engineering Technical Division under IEM, and technical consultant of failure analysis for MIMOS Semiconductor Sdn Bhd (Malaysia).

William Chen Bio

Email: [email protected]

Topics: Semiconductor and Electronics Industry Trends and Roadmap

William (Bill) Chen  holds the position of ASE Fellow & Senior Technical Advisor at ASE Group. Prior to joining the ASE, he was Director at the Institute of Materials Research & Engineering (IMRE) in Singapore, following a distinguished career at IBM Corporation. Bill is a past President of the IEEE Electronics Packaging Society. He is a Life Fellow of IEEE and a Fellow of ASME. He received the ASME InterPACK Achievement Award in 2007. In 2017 he received the ASME Ecellence in Mechanics Award.  In 2018, he received the IEEE Electronics Packaging Field Award, recognizing his contribution to electronic packaging, from research & development through industrialization. He received the IMAPS Daniel C. Hughes Memorial Jr. Award in 2022 for lifetime achievement to the microelectronics industry..

Bill chairs the Heterogeneous Integration Roadmap initiative, co-sponsored by 3 IEEE Societies (EPS, EDS & Photonics) together with SEMI & ASME Electronics & Photonics Packaging Division.

Ken Butler DL Bio

Email: [email protected]

Topics: Semiconductor test and reliability, AI/ML applications and edge computing for test and reliability, test challenges in advanced packaging and heterogeneous integration, product and test engineering, design for testability and automatic test pattern generation

Ken Butler is a semiconductor industry consultant with WattsButler LLC. Prior to that, he was with Advantest Cloud Solutions (ACS) for four years in both applications marketing and business development roles, and for 36 years with Texas Instruments working in DFT and test generation, semiconductor reliability, analog product and test engineering, and data analytics.  Ken has a BS from Oklahoma State University and an MS and PhD from the University of Texas at Austin, all in electrical engineering.  He is a Fellow of the IEEE, a Golden Core member of the IEEE Computer Society, and a Senior Member of the ACM. Ken also co-leads the EPS Heterogeneous Integration Roadmap chapter on test technology.

Tanja Braun Bio

Email: [email protected]

Topics:  Advanced Packaging, Heterogeneous Integration, Flip Chip, Chiplet, Fan-out Wafer and Panel Level Packaging.

Dr. Tanja Braun studied mechanical engineering at Technical University of Berlin with a focus on polymers and micro systems and joined Fraunhofer IZM in 1999. In 2013 she received her Dr. degree from the Technical University of Berlin. Tanja Braun is head of the department System Integration and Interconnection Technologies. Recent research is focused on Fan-out Wafer and Panel Level Packaging technologies. In 2021 she received the Exceptional Technical Achievement Award from IEEE Electronics Packaging Society (EPS) and the IMAPS Sidney J. Stein Award for her work in the field of Fan-out Wafer and Panel Level Packaging.

Tanja Braun is an active member of IEEE. She is member of the IEEE EPS Board of Governor (BOG) and the IEEE EPS VP of Conferences.

Chris Bower DL Bio

Email: [email protected]

Topics: Novel assembly methods, elastomer stamp micro-transfer-printing, heterogeneous integration, three-dimensional integration, manufacturing of micro-assembled displays and other large-format electronics.

Chris Bower is the Chief Technology Officer and co-founder of X Display Company (XDC).  His interests include three-dimensional integration of integrated circuits, heterogeneous integration of compound semiconductors onto non-native substrates and the fabrication of low-cost, large-format electronics using novel assembly methods.  Chris is co-author of over 150 publications and co-inventor of greater than 150 US patents.

Wendem T. Beyene Bio

Email: [email protected]

Topics: Design and SI/PI Analysis of High-Performance Memory Systems; Package Requirements for Data Rates of 112 Gbps and Beyond; Modeling and Analysis of heterogeneous interfaces; Applications of Machine Learning to Signal and Power Integrity Problems; Electrical Signaling—Modulation, Equalization, and Channel Design; Statistical Link Modeling and Simulation

Dr. Wendem Tsegaye Beyene has been employed, in the past, by IBM, Hewlett-Packard, and Agilent Technologies, Rambus, and Intel. He has been responsible for end-to-end signal and power integrity analysis of low-power SoC, Memory, CPU and FPGA including fabric and high-speed I/O subsystems as well as I/O modeling. He is currently an Analog & Mixed Signal Architect in Reality Labs at Meta Platforms. 

Dr. Beyene, an IEEE fellow, has authored or co-authored numerous refereed publications.  These publications covered various disciplines including die, package and system interconnect modeling and simulation, noise and jitter analysis, and optimization as well as machine learning.

He is currently a Senior Area Editor of IEEE Trans. on CPMT and serving as a Distinguished Lecturer for IEEE EPS society.  He is also an elected Associate Fellow of the Ethiopian Academy of Sciences. He has organized the annual IEEE EPS conference, DTMES, since 2022, in Ethiopia, Africa.

Mudasir Ahmad

Email: [email protected]

Topics: Architectures and electrical analysis/validation of advanced packaging and heterogenous integration technologies, electrical standards for advanced packaging, high-speed signaling, signal integrity

Kemal Aygün received the Ph.D. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign, Urbana, IL, USA, in 2002. In 2003, he joined the Intel Corporation, Chandler, AZ, USA, where he is currently an Intel Fellow and manages the High Speed I/O (HSIO) team in the Electrical Core Competency group. He has co-authored five book chapters, more than 90 journal and conference publications, and holds 96 U.S. patents. His research interests include novel technologies along with electrical modeling and characterization techniques for microelectronic packaging. Dr. Aygün was a recipient of the Semiconductor Research Corporation (SRC) Global Research Collaboration (GRC) Mahboob Khan Outstanding Mentor Award in 2008 and 2015 for his contributions in mentoring SRC GRC academic research projects. He was the General Chair of the 2020 IEEE Electrical Performance of Electronic Packaging and Systems Conference. He is an IEEE Fellow and has been acting as a Distinguished Lecturer for the IEEE Electronics Packaging Society (EPS); a co-chair of the EPS Technical Committee on Electrical Design, Modeling, and Simulation; and an associate editor for the IEEE Transactions on Components Packaging, and Manufacturing Technology.

Mudasir Ahmad

Email: [email protected]

Topics: Internet of Things (IoT), Advanced Packaging, 2.5D, Heterogeneous Silicon Photonics, Advanced Reliability (Thermomechanical, Mechanical Shock), Numerical Modeling, Advanced Thermal Solutions, Stochastic Analysis, Bayesian Inference, Machine Learning, Artificial Intelligence 

Mudasir Ahmad is the group manager of the System Reliability and Adv. Numerical Analysis Teams in the Global Hardware Quality and Reliability (GHQR) Organization in Google Technical Infrastructure (TI). Mudasir’s teams are responsible for system level hardware reliability of critical hardware deployed in all Google Data Centers. Before Google, he was a Distinguished Engineer/Senior Director at Cisco Systems, Inc. He has been involved with mechanical design, microelectronics packaging design and reliability analysis for more than 20 years. Mudasir is involved in developing new analytical/stochastic algorithms, experimental design, thermal and reliability characterization of next generation 3D packaging, System-in-Package Modules, Chiplets and Silicon Photonics. Mudasir was also involved with implementing IoT, Artificial Intelligence and Big Data Analytics to streamline Supply Chain Operations. Mudasir has delivered several invited talks on leading technology solutions internationally. 

Outside of Google, he is a Distinguished Lecturer of the Electronics Packaging Society of the IEEE (EPS) and participates in standards organizations and consortia such as IPC, JEDEC and ODSA. He was actively involved in the local EPS chapter of IEEE for several years; holding the positions of Secretary, Vice Chair and Chair of the Chapter. 

He received the internationally renowned Outstanding Young Engineer Award in 2012 from the IEEE. He received his M.S. in Management Science & Engineering at Stanford University, his M.S. degree in Mechanical Engineering from Georgia Institute of Technology and his B.S. from Ohio University. Mudasir has over 30 publications on microelectronic packaging, two book chapters, and 17 US Patents.

Ramachandra Achar Bio

Prof. Ramachandra Achar, Ph. D., P. Eng.

IEEE Fellow, Fellow EIC

Email:  [email protected]

URLwww.doe.carleton.ca/~achar

Ph: 613-520-2600, x5651

Topics: Fundamentals and Advances in Signal and Power Integrity Modeling; Modeling and analysis of large multi-port scattering parameters based on Tabulated data; Parallel Algorithms and Methods for Signal and power Integrity Analysis

Prof. Achar currently is a professor in the department of electronics engineering at Carleton University, Ottawa, Canada. He is a Fellow of IEEE as well as of Engineers Institute of Canada. He is a leading expert on signal and power integrity modelling and analysis, and a consultant for several leading industries in the field. Dr. Achar has published over 250 peer-reviewed articles in IEEE international transactions/conferences, six multimedia books on signal integrity and five chapters in different books. He has delivered over 100 invited talks in the field of signal and power integrity in global forums. His research interests include signal/power integrity modeling and analysis, EMC/EMI analysis, circuit simulation, parallel and numerical algorithms, microwave/RF algorithms and mixed-domain analysis.

Prior to joining Carleton university faculty (2000), he served in various capacities in leading research labs, including T. J. Watson Research Center, IBM, New York (1995), Larsen and Toubro Engineers Ltd., Mysore (1992), Central Electronics Engineering Research Institute, Pilani, India (1992) and Indian Institute of Science, Bangalore, India (1990). 

Dr. Achar received several prestigious awards, including Bharat Guarav Award (2014), Carleton university research achievement awards (2010 & 2004), NSERC (Natural Science and Engineering Research Council) doctoral medal (2000), University Medal for the outstanding doctoral work (1998), Strategic Microelectronics Corporation (SMC) Award (1997) and Canadian Microelectronics Corporation (CMC) Award (1996). He was also a co-recipient of the IEEE advanced packaging best transactions paper award (2007) and IEEE T-CPMT best transactions paper award (2013). His students have won numerous best student paper awards in international forums.

Prof. Achar currently serves as a Distinguished Lecturer of the IEEE Electronic Packaging Society and Chair of the Distinguished Lecturer of Program for the IEEE EMC Society. He currently serves or previously served on the executive/steering/technical-program committees of several leading IEEE international conferences, such as EPEPS, EDAPS and SPI etc. and in the technical committees, EDMS (TC-12 of EPS).

Dr. Achar previously served as a Distinguished Lecturer (DLP) of the IEEE Circuits and Systems Society (CASS) (2011, 2012) as well as IEEE EMC Society (2015, 2016), and a guest editor of IEEE Transactions on CPMT, for two special issues on “Variability Analysis” and “3D- ICs/Interconnects”. He also previously served as the General Chair of HPCPS (IEEE International Workshop on High-Performance Chip Package and Systems 2012-2016), General Co-Chair of SIPI- 2016 (Signal Integrity and Power Integrity Conference), General Co-Chair of NEMO-2015 (Electromagnetic and Multi-physics based modeling, simulation and optimization for RF, microwave and terahertz applications), General Co-Chair of IEEE international conference on Electrical Performance of Electronic Packages & Systems (EPEPS-2010, 2011), and as an International Guest Faculty on the invitation of the Dept. of Information Technology of Govt. of India, under the SMDP-II program. He is a founding faculty member of the Canada-India Center of Excellence, chair of the joint chapters of CAS/EDS/SSC societies of the IEEE Ottawa Section.

Prof.  Achar (S’95-M’00-SM’04-FM’13) received the B. Eng. degree in electronics engineering from Bangalore University, India in 1990, M. Eng. degree in micro-electronics from Birla Institute of Technology and Science, Pilani, India in 1992 and the Ph.D. degree from Carleton University in 1998.

Vempati Srinivasa Rao Bio

Mr. Vempati Srinivasa Rao is Director at Heterogeneous Integration, Institute of Microelectronics (IME), Singapore. He has over 20 years of R&D experience in microelectronics packaging, assembly, reliability, and failure analysis. He leads HI department to develop advanced wafer level packaging platform technologies and process/integration capabilities such as fine pitch multi-layer RDL, TSV interposer, W2W and C2W Hybrid Bonding required for heterogeneous chiplet integration. He has authored or co-authored more than 80 journal and conference publications in electronic packaging area. His research interest includes chiplet integration using Fan-out wafer level packaging, 2.5D packaging, 3D chip stacking. He received a Masters Degree in Mechanical Engineering with Material Science Specialization from the National University of Singapore, and Bachelor Degree in Metallurgical Engineering from the National Institute of Technology, Warangal, India

Vipul Patel bio

Dr. Vipul Patel is currently serving as a principal engineer in the Global Supplier Management group at Cisco Systems. He joined Cisco through the acquisition of Lightwire in 2012, a company he co-founded in 2002. Dr. Patel has a proven track record of successfully bringing innovative photonics technologies from concept to market introduction and production in both startup and large company settings. His extensive supply chain experience involves managing suppliers across the US, Europe, and Asia, particularly for silicon photonics-related products.

During his tenure at Lightwire, Dr. Patel was a key technical contributor to the development of the industry’s first IEEE-compliant 100G CPAK transceivers, utilizing groundbreaking silicon photonics technology. This innovation significantly bolstered Cisco’s leadership position in optical transceivers post-acquisition. At Cisco, Dr. Patel continues to focus on next-generation technology development and the associated supply chain for photonics products.

Before Lightwire, Dr. Patel co-founded LightMatrix Technologies, which focused on developing thin film-based products for the fiber-optic communication industry. Prior to LightMatrix, he managed the Silicon Device Group at Sarnoff Corporation, overseeing R&D programs for government and commercial clients across various technologies, including CCDs, BiCMOS, SOS, MEMS, and TFT displays.

Dr. Patel holds a Ph.D. in Electrical Engineering and possesses deep knowledge of semiconductor processes and packaging. He is an inventor with 126 issued US patents and 17 pending applications. Additionally, he has contributed a book chapter on plasma etching for the “Handbook of Vacuum Technology: Modern Methods and Techniques.

Subu Iyer Bio

Subramanian S. Iyer (Subu) is Distinguished Professor and holds the Charles P. Reames Endowed Chair in the Electrical Engineering Department and a joint appointment in the Materials Science and Engineering Department at the University of California at Los Angeles. In 2023-4, he was on assignment to the US Department of Commerce as Director of the National Advanced Packaging Manufacturing Program, where he laid the foundational strategy for the national packaging imperative. He is the founding Director of the Center for Heterogeneous Integration and Performance Scaling (UCLA CHIPS). Prior to that he was an IBM Fellow. His key technical contributions have been the development of the world’s first SiGe base HBT, Salicide, electrical fuses, embedded DRAM and 45nm technology node used to make the first generation of truly low power portable devices as well as the first commercial interposer and 3D integrated products. Since joining UCLA, he has been exploring new packaging paradigms and device innovations that may enable wafer-scale architectures, in-memory analog compute and medical engineering applications.   He is a fellow of IEEE, APS, iMAPS and NAI as well as a Distinguished Lecturer of IEEE EDS and EPS. He is a Distinguished Alumnus of IIT Bombay and received the IEEE Daniel Noble Medal for emerging technologies in 2012 and the 2020 iMAPS Daniel C. Hughes Jr Memorial award and the iMAPS distinguished educator award in 2021. Prof. Iyer was also Prof. Ramakrishna Rao VisitingChair Professor at IISc, Bengaluru.

Norman Chang Bio

Norman Chang co-founded Apache Design Solutions in February 2001 and currently serves as Ansys Fellow and Chief Technologist at Electronics, Semiconductor, and Optics BU, ANSYS, Inc. He is currently leading AI/ML and security initiatives at ANSYS. Dr. Chang received his Ph.D. in Electrical Engineering and Computer Sciences from University of California, Berkeley. He holds 32 patents and has co-authored over 60 IEEE papers and a popular book on ”Interconnect Analysis and Synthesis” by Wiley-Interscience at 2000. Dr. Chang is an IEEE Fellow for his contribution on ”Leadership and contributions to the physical-level sign-off of Electronic Design Automation for SoC/3DIC”. He is also a recipient of 2024 ”Distinguished Entrepreneur of the Year” Award from Chinese Institute of Engineers (CIE). He actively engages in industry committees such as IEEE EDPS (Electronic Design Process Symposium) and SI2. He also contributed a section in HIR Roadmap Chapter 20 on Thermal at 2023.

J Lu Bio

Jimmy Lu is the Deputy General Director at the Electronic and Optoelectronic System Research Laboratories (EOSL) of the Industrial Technology Research Institute (ITRI) in Taiwan. He leads a team of over 200 engineers, focusing on IC design, electronic design automation, system software, and deep learning for AIoT applications. His current research initiatives are aimed at AI processor design, covering areas such as AI hardware accelerators, compiler software, algorithms, and chiplet-based system architectures.

Erik Jung Bio

Erik Jung has a background in “physics”, “physical chemistry” and “physics in medicine” from the University of Kaiserslautern, he joined Fraunhofer IZM in 1994. Heading the group Advanced Microsystem Assembly, he developed processes in flip chip and chip embedding technologies eventually expanding his research field into the MEMS/NEMS packaging and initiated IZM´s MEMS research program in 2005.

Staying from 2007 to 2008 as a research delegate at the University of Utah he was involved in the packaging of a wireless brain computer interface, establishing the focus group on Medical Microsystems upon his return to the Fraunhofer IZM. He was appointed as head of the business sector on medical technologies in 2009.

Madhavan Swaminathan Bio

Madhavan Swaminathan is the Department Head of Electrical Engineering and is the William E. Leonhard Endowed Chair at Penn State University. He was previously worked at Georgia Institute of Technology for 28 years. An IEEE Fellow, Swaminathan is Department Head of Electrical Engineering, William E. Leonhard Endowed Chair, and Director of CHIMES (an SRC JUMP 2.0 Center), College of Engineering, Penn State University, Pennsylvania, USA

Chris Bailey Bio

Christopher Bailey is a tenured professor at Arizona State University, Tempe, Arizona.  Prior, he was Professor of Computational Mechanics and Reliability at the University of Greenwich, London, United Kingdom. Chris received my PhD in Computational Modelling from Thames Polytechnic in 1988, and an MBA in Technology Management from the Open University in 1996. Before joining Greenwich in 1991, he worked for three years at Carnegie Mellon University (USA) as a research fellow in materials engineering.

My research has resulted in over 250 publications. I am currently an Associate Editor for the CPMT Transactions and have been a guest editor on the journal of Soldering and Surface Mount Technology. I am also a committee member of the Innovative Electronics Manufacturing Research Centre (IeMRC) in the UK and have participated in a number of UK Government sponsored overseas missions to promote collaboration and review electronic packaging technologies. Recently I became a member of the working group writing a new IEEE standard for Prognostics and Health Management for Electronic Systems.

Braunisch Bio

Henning Braunisch received the Ph.D. degree in electrical engineering and computer science from MIT in 2001. He has since been with Intel Foundry Technology Research in Chandler, Arizona, where he works as Principal Engineer on research in microelectronic packaging and university research management. He is currently serving as an Intel assignee as Director, Semiconductor and Packaging Research, SRC/NIST SMART USA Institute. Dr. Braunisch’s publications and patents, including 111 US patents, have more than 3,400 citations and an h-index of 30 as reported by Google Scholar. He is a Fellow of the IEEE.

Nagisetty Bio

Ramune Nagisetty is a Fellow in semiconductor technology research at NATCAST. Her prior 29 years at Intel include a decade in transistor technology development leading innovations in silicon strain engineering, as well as pathfinding for hiK metal gate and FinFET. Informed by her background in silicon technology development, she led the cross-Intel System Technology Co-optimization Pipeline across technology, design, and architecture, including chiplets, advanced packaging, power delivery, memory stacking, and 3D system modeling. She also led external engagements and deployed test chips across all of Intel’s leading technology nodes in development to quantify and mitigate unwanted process design interactions, local layout effects, and layout sensitive defects.

Ramune earned a BSEE from Northwestern University in 1991 and an MSEE specializing in solid state physics from the University of California, Berkeley in 1995. She has authored fourteen technical publications and has fifteen issued or pending patents related to device physics, high performance process technology, and technology usage models. Her vision for a new industry-scale chiplet ecosystem has been featured in Wired Magazine, AnandTech, and IEEE Spectrum.

Jason Killgore Bio

Jason Killgore is the group leader for the nanoscale reliability group in the applied chemicals and materials division at NIST. His research interests span a full range of nanoscale microscopy methods for applications ranging from bioprinting to semiconductor packaging.

Marcelo Davanco Bio

Marcelo Davanco is a Project Leader in the NIST Microsystems and Nanotechnology Division. His current research interests are in the design, fabrication and characterization of integrated photonic interfaces to single solid-state quantum light emitters, towards applications in quantum information science and technology. He has co-authored over 60 journal papers and two book chapters, holds two patents, and has made many contributions to a wide range of research topics, such as photonic crystals and metamaterials, heterogeneous integrated photonic devices, integrated nonlinear optics and cavity optomechanics, and on-chip integrated quantum light emitters.Marcelo has B.S. and M.S. degrees in Electrical Engineering from the State University of Campinas (UNICAMP), Brazil, and a Ph.D. in Electrical and Computer Engineering from the University of California Santa Barbara in 2006.

John Scott Bio

Dr. John Henry Scott is a Physicist in the NIST Materials Measurement Science Division. His work has focused on the elemental and structural characterization of heterogeneous materials in 2D and 3D using electron and ion beams, x-rays, and diffraction methods at spatial resolutions from sub-nanometer to micrometers. John Henry earned a BS in Physics from Caltech, an MS and PhD in Physics from Carnegie Mellon University, and an MS in Biotechnology from The Johns Hopkins University. His Dept of Commerce awards include two Gold Medal Awards and two Bronze Medal Awards, including an individual award for “Exceptional innovation in dimensional and chemical measurements at the nanoscale”.

James Booth Bio

James C. Booth joined the National Institute of Standards and Technology as a physicist in 1996, and currently leads the Guided Wave Electromagnetics Group within the Communications Technology Laboratory. He received the Ph.D. degree in Physics from the University of Maryland. Research interests at NIST include material and component measurements for advanced wireless communications; on-wafer measurements and standards for advanced microelectronics and hardware security applications; and novel microfluidic chip-based techniques exploiting electromagnetic effects for chemistry and biochemistry.

Xiaohong Gu Bio

Xiaohong Gu is a Materials Research Engineer and currently serves as the acting leader of the Infrastructure Materials Group at the NIST Engineering Laboratory. She received her Ph.D. from the Department of Polymer Science and Engineering at Nanjing University, China, and joined NIST in 1998. Her field of interest includes accelerated laboratory aging, reliability testing, degradation characterization, and service life prediction of polymeric materials for photovoltaic and semiconductor applications. She has published over 100 papers and won numerous awards in the areas of photovoltaics, polymer degradation and characterization, and lifetime prediction.

Jason Gorman Bio

Jason J. Gorman is the group leader for the Photonics and Optomechanics Group in the Microsystems and Nanotechnology Division at the National Institute of Standards and Technology (NIST). He joined NIST after being awarded a National Research Council Postdoctoral Research Associateship. He received a B.S. in aerospace engineering from Boston University, and an M.S. and Ph.D. in mechanical engineering from The Pennsylvania State University. His work is currently focused on the development of low-loss micromechanical resonators and optical microcavities and their combined use in integrated optomechanical sensors and frequency sources. Applications of interest include inertial sensing, ultrasound detection, micromechanical clocks, and RF photonic devices.

John Shalf Bio

John Shalf (URL) is the Department Head for Computer Science at Lawrence Berkeley National Laboratory. Behind the scenes, Shalf has lent his expertise to lay the groundwork for executing the US government’s exascale ambition since 2009. He also formerly served as the Deputy Director for Hardware Technology on the US Department of Energy (DOE)-led Exascale Computing Project (ECP) before he returned to his department head position at LBNL.

He has co-authored over 100 peer-reviewed publications in parallel computing software and HPC technology, including the widely cited report “The Landscape of Parallel Computing Research: A View from Berkeley” (with David Patterson and others). Before coming to Berkeley Laboratory, John worked at the National Center for Supercomputing Applications and the Max Planck Institute for Gravitation Physics/Albert Einstein Institute (AEI), where he co-created the Cactus Computational Toolkit.

Sarah Smith Bio

Srilatha (Bobbie) Manne bio

Srilatha (Bobbie) Manne is a Senior Fellow in the Research and Advanced Development group at Advanced Micro Devices (AMD). She received her PhD from the University of Colorado, Boulder, and has worked on low-power/high-performance architecture for over two decades in both industrial research labs and product teams at companies such as AMD, Microsoft, and Intel. More recently, she has investigated efficiency and sustainability in hardware design and at scale computing. She has over 30 publications and is a co-inventor on nearly 40 patents pending or granted.

Bio Kroehnert

Steffen Kroehnert (M: 2011) is a well-known component of the Packaging Community for more than 10 years. He is President & Founder of ESPAT-Consulting based in Dresden, Germany. Steffen is providing a wide range of consulting services around Semiconductor Packaging, Assembly, Interconnect Technologies and Test, mainly for customers in Europe. Utilizing his large network in industry, institutes and academic, he also supports small- and medium-sized companies as well as innovative Start-ups to find the right packaging solutions for their products and setup the supply chain from prototypes to small series and High Volume Manufacturing (HVM). Until June 2019, he worked for 22 years in different R&D, engineering and management positions at large IDMs and OSATs in Germany and Portugal, namely Siemens Semiconductors Regensburg (1997-1999), Infineon Technologies Regensburg and Dresden (1999-2006) and Qimonda Dresden and Porto (2006-2009), where Steffen was instrumental in developing FBGA packaging technology for DRAM products. As Director of Technology, he helped setting up and making visible the company NANIUM Porto and Dresden (2009-2017), the largest OSAT in Europe, where Steffen has been heading R&D during introduction of System-in-Package (SiP) and technology transfer and scaling from 200mm to 300mm reconstituted wafer format of the leading Fan-Out Wafer Level Packaging Technology embedded Ball Grid Array (eWLB) from Infineon Technologies. After acquisition of NANIUM by Amkor Technology served as Senior Director Technology Development in Porto and Dresden (2017-2019) working with the European Business Development team.  Steffen founded and chaired the European SEMI integrated Packaging, Assembly and Test – Technology Community (ESiPAT-TC) inside SEMI Europe from 2016-2020, serving now as co-chair. His excellence in developing and innovating electronics packaging for semiconductor devices has resulted in authoring and co-authoring of 23 patent filings and many technical papers in the field of Packaging Technology. He co-edited the book “Advances in Embedded and Fan-Out Wafer Level Packaging Technologies”. Since 2011, Steffen is co-chair of the Advanced Packaging Conference (APC) committee at SEMICON Europe, which is built of 22 packaging experts from European industry, institutes and academic. Steffen is active member of several technical and conference committees at IEEE EPS, IMAPS, SMTA and SEMI. He holds a M.Sc. degree in Electrical Engineering and Microsystems Technologies from the Technical University of Chemnitz, Germany.

Bio Chen

WILLIAM T. CHEN (M’92, SM‘03, F’06) received his engineering education at University of London (B.Sc), Brown University (M.Sc) and Cornell University (PhD).  He joined IBM Corporation at Endicott New York in 1963.

At  IBM  he  worked  in  a  broad  range  of  IBM microelectronic packaging products. He received IBM Division President Award for his leadership and innovation in Predictive Modelling on IBM products.    He was elected to the IBM Academy of Technology for his contributions to IBM Products and Packaging Technologies. He retired from IBM in 1997.  He joined the Institute of Materials Research and Engineering (IMRE) in Singapore, to initiate research in microelectronic packaging materials and processes.  He was appointed to the position Director of the Institute (IMRE) steering the  growth  in  people, funding and research facilities and research direction for  IMRE  to  become  the  leading  materials science and engineering  research  center  in the ASEAN region. In 2001 he joined ASE Group, where he holds the position of ASE Fellow and Senior Technical Advisor.  In this assignment he has responsibilities for guidance to technology strategic directions for ASE Group.

He is Senior Past President of the IEEE/CPMT Society. He is the Co-Chair of the ITRS Assembly and Packaging Roadmap Technical Working Group.  He is chair of the Semicon West Packaging Committee. He has been elected to a member of the iNEMI Board. He is a member of the Technology Committee of GSA.

He has been elected to Fellow of IEEE and Fellow of ASME.  He has served as an  Associate  Editor  of ASME Journal of Electronic Packaging, and IEEE/CPMT Transactions.

Bio Tay

ANDREW TAY (M1991, SM2019, F2023) is currently a Visiting Scientist at the Singapore Hybrid-Integrated Next-Generation μ-Electronics Centre (SHINE), National University of Singapore (NUS). Prior to this he was a Senior Research Fellow at the Singapore University of Technology and Design and Professor in the Department of Mechanical Engineering, NUS. He obtained his B.E. (Hons I and University Medal) and PhD in Mechanical Engineering from the University of New South Wales, Australia. His research interests include thermo-mechanical reliability, thermal management of electronics and EV battery systems, reliability of solar photovoltaic modules and fracture mechanics. To date he has published more than 250 technical papers, 4 book chapters, 7 keynote presentations, 11 invited presentations and 3 panel discussions.

Dr Tay was the General Chair of the 1^st Electronics Packaging Technology Conference (EPTC) in 1997. In 2006 he was appointed the inaugural Chairman of the EPTC Board, and is currently serving as its Chairman. He has been in the Executive Committee of the IEEE Singapore RS/EPS/EDS Chapter since 2000 and was its Chairman from 2010-2011 and 2018-2019. He has been involved in the international advisory boards and program committees of many electronics packaging conferences including DTIP, ECTC, EMAP, EPTC, EuroSimE, HDP, ICEPT, IEMT, IMPACT, InterPack, ITHERM and THERMINIC.

He was an Associate Editor of the ASME Journal of Electronic Packaging, an editorial board member of several journals including Microelectronics Journal and Finite Elements in Analysis and Design, and a guest editor of special issues of Microelectronics Reliability Journal, and Journal of Electronics Packaging. He is currently Co-Editor-in-Chief, Encyclopedia of Packaging Materials, Processes, and Mechanics.

He was a member of the EPS Education Committee from 1998 to 2007, and the coordinator of the Singapore Economic Development Board’s Specialized Manpower Program in Electronics Packaging and Wafer Fabrication in NUS. He has been awarded competitive research grants exceeding $14 Million for electronics packaging projects.

He was awarded the 2019 IEEE EPS David Feldman Outstanding Contribution Award, the 2012 IEEE EPS Exceptional Technical Achievement Award, the 2012 IEEE EPS Regional Contributions Award, the 2004 ASME Electronics & Photonics Packaging Division Engineering Mechanics Award, the 2000 IEEE Third Millennium Medal and the 2000 Special Presidential Recognition Award.

Yu-Po Wang Bio

Dr Yu-Po Wang (M ’21) is VP of central R&D of SPI since 2022. His main research interests include package development, material selection, design optimization within the field of electronic packages.  He is a BoG member of IEEE EPS from 2021 to 2024.  He helped organize many international symposia on electronic package technology.  He serves as guest editors for the Applications of Data Sciences in Semiconductor Industry: Design, Manufacturing, Packaging and Testing.

Wang received his Ph.D. in Mechanical Engineering from Binghamton University, State University of New York in 1997. He joined Gintic Institute of Manufacturing Technology, Singapore as a research fellow in 1997.  He retuned to native country, Taiwan, to join Siliconware Precision Industrial Ltd (SPIL) in 1998 as a R&D senior engineer. He became the vice president of central R&D (CRD) in 2022 throughout the level of managers and directors within CRD during his 20 plus years of service.  He also servs as an adjunct professor of College of Science and Technology at National Chi Nan University, Taiwan.  Wang was rewarded the top 10% best instructor within University in 2022.

Wang holds 83 US and Taiwan patents. Wang is considered the leading experts on the package structure design and applications for electronic packaging, and has given more than 30 invited or keynote lectures in the international conferences.

Yik Yee Tan Bio

Yik Yee Tan Ph.D.(M ’08; SM ’14) is a Senior Technology & Market Analyst, Semiconductor Packaging & Assembly at Yole Group, within the Semiconductor Manufacturing & Global Supply Chain Division. Dr. Tan holds a Ph.D. in Engineering from Multimedia University (MMU, Malaysia). She has more than 25 years of experience in semiconductor packaging. Based on her technical expertise and market knowledge, she develops technology & market reports and is engaged in dedicated custom projects. Prior to Yole, Dr. Tan worked as a failure analyst and interconnect principal at Infineon Technologies (Malaysia) and later as an open innovation senior manager at Onsemi (Malaysia). While at onsemi, Yik Yee was deeply involved in numerous innovative advanced packaging projects. She published more than 30 papers and hold 3 patents. Recently, she is the award winner for IEEE EPS – Regional Contribution Award in Region 10 (Asia, Pacific) 2024 and IEEE Malaysia Section – Outstanding Industry Volunteer Award 2024.

Dr Tan played a pivotal leadership role within IEEE EPS Malaysia Chapter, orchestrating its growth and secure prestigious “Best Medium Chapter 2022” award from IEEE Malaysia Section. Having occupied critical positions in EPS Malaysia and various conferences, she has successfully introduced numerous impactful technical sessions to Malaysia technical community, leveraging her network to bring renowned speakers from the packaging community globally.

Shinya Takyu Bio

Shinya Takyu  (M ’12) received the B.E. from The University of Electro-Communications, Tokyo, Japan in 1991. After graduated, he joined the Process & Manufacturing Engineering Center in TOSHIBA Corporation and had been engaged in the development of semiconductor packaging process; Dincing, Back Griding, Pick-Up, and Flip Chip. He developed the “Dicing Before Grinding” process; well known as DBG and his proceeding about DBG on ECTC 2006 was referred by ITRS 2007, ITRS 2009, and SiP Whitepaper V9.0. DBG  has been contributed to the thin IC card chip and the 17 layers stack NAND Flash Memory package for mass production. DBG is the de-fact standard process for thin devices now.

In April 2014, he moved his position to a project manager, LINTEC Corporation in Japan. Since then, he has been worked for the development of novel processes using new tape materials and equipment. In 2019, he started up his own new group named “Next Generation Innovation Group”. He has been working for the advanced packaging process for Fan-Out, chiplet, and so on and new material for well-being. He is now an assistant general manager of LINTEC Corporation.

He is a member of IEEE EPS (Electronics Packaging Society), JIEP (The Japanese Institute of Electronics Packaging) and The Institute of Electronics, Information and Communication Engineers. He was the general chair of ICSJ2017 (IEEE CPMT Symposium Japan 2017). He was the secretary of EPS Japan Chapter (2019-2020) and the vice chair of EPS Japan Chapter (2021-2022). Now he is the chair of IEEE EPS Japan Chapter (2023-present).

Yoichi Taira Bio

Yoichi Taira (M ’89; LS ’20) obtained a Ph. D. in Physics in 1980 from the University of Tokyo. He then served as an associate professor at the Institute for Laser Science of the University of Electrocommunications, Tokyo, Japan. In 1988, he joined IBM Research Laboratory in Tokyo. He worked in the Science and Technology Department of IBM Research for 26 years and moved to Keio University in 2016. He has been an IEEE Member since 1988.

He is a scientist and engineer in electronics, particularly optical science and systems packaging. His technical achievements include VLSI circuit design, VLSI technology, laser science, flat panel information display technology, electronics packaging process and materials, VLSI packaging, and optical interconnect technology.

He has also accomplished many technical accomplishments in various technical areas. Some of the accomplishments include 1) pioneering work on picosecond photon echo study (Yajima and Taira JPSJ 1979); 2) CW deep UV coherent source (CLEO Invited talk 1993); 3) Discovery of vision effect (blurring of moving object images) of active matrix liquid crystal flat panel displays (Society of Information Display IDRC, 1997); 4) High-performance thermal interface material based on vertically aligned graphite for chip cooling (2008 IEEE ECTC 2008); and 5)  Optical packaging of silicon nanophotonics using polymer optical waveguides (IEEE Photonics Journal 2014).

He served a lecturer on the optical transceiver packaging technology at Optical Fiber Communications Conference (OFC) in 2020, 2021, 2022, and 2023.  He served a lecturer on the optical data communication technology at APCS Technology Seminar of the Semicon Japan 2023.

He has shown leadership by serving as 1) the Program Chair of IEEE Systems Japan Workshop (2017); 2) general Chair of Annual Meeting of Japan Institute of Electronics Packaging (2017); 3) the Chair of IEEE Electronics Packaging Society (EPS) Japan Joint Chapter (2017-2018); and 4) the board member (2008-2012), Editor in Chief (2011-2012of Japan Institute of Electronics Packaging and is serving as Board of Governor of IEEE EPS (2018-2023).  He received the Outstanding Achievement Award from Japan Institute of Electronics and Packaging in 2021, and the Regional Contribution Award by Electronic Packaging Society, IEEE in 2023.

Sarah Eunkyung Kim Bio

Sarah Eunkyung Kim, Ph.D. (M ’18; SM ’22) is a professor in the Department of Semiconductor Engineering at Seoul National University of Science and Technology (Seoul Tech). She holds a B.S. in Materials Science and Engineering from Rensselaer Polytechnic Institute, an M.S. from the Massachusetts Institute of Technology, and a Ph.D. from Rensselaer Polytechnic Institute. Dr. Kim’s career spans over two decades, during which she has made significant contributions to the field of semiconductor engineering, particularly in advanced packaging technologies. Before joining Seoul Tech, she worked at Samsung Electronics, Intel, and the Korea Institute of Science and Technology. At Intel, she specialized in BEOL interconnect including thick metal interconnects, 3D integration, and die-package interface development. At Seoul Tech, Dr. Kim’s research focuses on Cu hybrid bonding, wafer-level packaging, and advanced packaging interconnects. She holds numerous US and Korean patents and has published extensively in international journals, and her dedication to innovation and education has earned her numerous honors and awards.

Benson Chan Bio

Benson Chan (M ’20) received his B.S. in Mechanical Engineering in 1981 and M.S. in Engineering Science in 1987 from Rensselaer Polytechnic Institute. Mr. Chan has solid background in Electronic Packaging, with strong emphasis in High Speed Applications and Electrical Connector design. Mr. Chan had a diverse career with IBM for 22 years in the areas of Process Engineer, Design Engineer and Development Engineer. At IBM he was an Advisory Engineer in the Connector Development group responsible for developing custom connectors used in I, P and Z series mainframes for IBM. He was also the lead mechanical engineer for the development of the first 10Gbps x 12 optical transceiver in IBM. In the last 4 years at IBM, he was a taskforce lead managing members around the world responsible for correcting problems with LGA connectors for Z series systems as well as the 10K RPM hard drives for IBM.

After IBM, he was with Endicott Interconnect Technologies for 12 years as a Chief Scientist. At EIT, he was the principle investigator for the DARPA Terabus III program, responsible for the design and build of a flexible optical waveguide capable of 25Gbps per channel with 48 channels interconnecting 2 hybrid optical modules. For a large DoD project, he provided all packaging options to dense pack the maximum number of processing elements into a given space, he also provided thermal solutions to support a 72KW cabinet.  Mr. Chan holds 54 Patents in the fields of electronic packaging and advanced Connectors. He has 18 published papers in the fields of electronic packaging and connectors (ECTC, iMAPS, Photonics Journal, Fleck Research). Mr. Chan is active in iMAPS as a past director and has served for 6 years as a track chair for the iMAPS Symposium; he is an iMAPS Fellow and the president of the Empire Chapter of iMAPS. He has served many roles in IEEE EPS, he is currently the chair of the Binghamton Chapter of IEEE EPS as well as the chair of the IEEE EPS Technical Committee on Emerging Technologies. For ECTC, he is on the sub-committee on Emerging Technology and was the chair of the committee in 2019-2020. He served his first term in the IEEE EPS Board of Governors from 2022 to 2024 for Regions 1-7&9. He is very active in the IEEE EPS Heterogeneous Integration Roadmap, serving as a co-chair for the Mobile chapter, a member in the Single / Multichip chapter, the MEMS chapter and the Additive Manufacturing technology chapter.

Jain Bio

Dr. Aakrati Jain (M’21) is a Hardware Engineer at IBM Research’s AI Hardware Center in Albany, NY. Her work has a strong focus on advanced packaging for Heterogeneous Integration in high-computational applications like AI and Machine Learning. Dr. Jain holds a B. Tech. degree in Mechanical Engineering (2013) from Indian Institute of Technology Kharagpur, India, and a direct Ph.D. in Mechanical Engineering (2019) with a specialization in heat transfer and electronics cooling from Purdue University in West Lafayette, Indiana. Since joining IBM Research in January 2020, Dr. Jain has been actively involved in various aspects of packaging, particularly in heat transfer, cooling, and thermal characterization of electronic packages for high-bandwidth applications. Her research endeavors revolve around understanding the factors influencing the thermal performance of electronic packages, aiming to enhance their efficiency and reliability. 

In addition to her role as a Hardware Engineer, Dr. Jain holds the position of Lead of Operations for IBM’s Chiplet Packaging Lab. She is responsible for enabling bond and assembly processes, and her expertise lies in laser-based wafer separation techniques. Dr. Jain also serves as the technical lead in IBM’s joint development endeavors with their dicing technical partner. In this role, she spearheads the definition and strategic direction of wafer separation processes for IBM Research’s advanced packaging initiatives.

Throughout her career, Dr. Jain has actively contributed to the field of electronics cooling and packaging. Her research has been published in renowned journals and presented at international conferences such as IJHMT, IEEE ECTC, and ITherm. She has authored more than 15 peer-reviewed articles and filed multiple technical patents, showcasing her innovative thinking and contributions to the industry.

Outside of her research, Dr. Jain actively participates in professional organizations and community initiatives. She currently serves as the Secretary for IEEE EPS’s newly-formed Mid-Hudson Valley (MHV) chapter. Under her leadership, the chapter has successfully organized two well-attended Mini-Colloquiums, featuring industry experts who shared insights on relevant topics in electronics packaging. Under her tenure, the chapter also organized a lecture series and a virtual seminar. Additionally, she serves as an industry liaison for the Semiconductors Research Center (SRC), where she mentors students and selects research projects in the packaging domain, with a specific focus on materials and technologies for thermal management and cooling of advanced packages.

Higurashi Bio

Eiji Higurashi (M’10-SM’17) received the M.E. and Ph.D. degrees from Tohoku University, Sendai, Japan, in 1991 and 1999, respectively. From 1991 to 2003, he was with Nippon Telegraph and Telephone Corporation (NTT), Japan. From 2003 to 2017, he was an Associate Professor with The University of Tokyo, Japan. From 2017 to 2022, he was a team leader or a group leader with The National Institute of Advanced Industrial Science and Technology (AIST). Since 2022, he has been a Professor in the Department of Electronic Engineering, School of Engineering, Tohoku University.

He is a Senior Member of the Institute of Electrical and Electronics Engineers (IEEE), the Institute of Electrical Engineers of Japan (IEEJ), and the Institute of Electronics, Information, and Communication Engineers (IEICE). He is a member of the Japan Institute of Electronics Packaging (JIEP), the Japan Society for Precision Engineering (JSPE), the Japan Society of Applied Physics (JSAP). He is an active member of the IEEE EPS Japan Chapter and served as the Secretary from 2013 to 2014, the Vice Chair from 2019 to 2020, and the Chair from 2021 to 2022. He has served as the General Chair of International Conference on Electronics Packaging (ICEP) from 2020 to 2021. He served as the Editor-in-Chief of Editorial Committee of the Journal of The Japan Institute of Electronics Packaging and has served as an Editor-in-Chief of Editorial Committee of the Transactions of The Japan Institute of Electronics Packaging.

He has authored or co-authored more than 300 journal and conference papers. He was a recipient of the Igarashi Award from the Sensors and Micromachine Subsociety of the Institute of Electrical Engineers of Japan in 2002, the Okawa Publications Prize from the Okawa Foundation for Information and Telecommunications in 2003, the Ichimura Academic Award from the New Technology Development Foundation in 2008, the International Conference on Electronics Packaging Best Paper Award in 2013 and 2016, 18th International Conference on Solid-State Sensors, Actuators and Microsystems (Transducers 2015) Outstanding Paper Award in 2015.

Bio Yang

JIN YANG (M: 2009, SM: 2017) is a thermal architect with Intel Corporation located in Oregon USA. His research areas include, electronic and photonics packaging, and advanced package, component and system thermal management and microelectronics cooling. He has over 10 years of experiences in the areas of microelectronics manufacturing, electronic packaging and electronics cooling since he obtained his PhD degree in 2008. He was a senior staff engineer with Assembly, Test Technology Development (ATTD), Intel Corporation focused on next-generation disruptive thermal-mechanical technology development for meeting novel electronic package needs. He holds 14 US patents in the areas of electronic packaging and microelectronic cooling and has published over 30 peer-reviewed journal and conference papers. Prior to join Intel Corporation, Jin Yang obtained a PhD degree from Georgia Tech in Atlanta in the area of electronic packaging. Before that, he obtained his master degree and bachelor degree from Texas A&M University (College Station, TX) and Tsinghua University (Beijing, China) respectively.

Jin is an elected IEEE senior member and serves technical sub-committee chair of IEEE EPS (electronic packaging Society) ECTC and track chair of IEEE ITHERM. He has been a member of IEEE ECTC Assembly and Manufacturing Technology (AMT) committee since 2010 and served as assistant chair and chair for this committee for 2019 and 2020 respectively. During the last four years, he has served as track chair for IEEE IHTERM since 2016.

Outside IEEE, Dr. Yang has a long history of continued service to ASME community in the area of electronic and photonic packaging and has taken a leadership role in ASME Electronic and Photonic Packaging Division (EPPD). He serves as General Chair of InterPACK’2020 conference, flagship conference of ASME Electronic and Photonic Packaging Division (EPPD) and served as program co-chair and track chair in the last four years. He is Associate Editor of ASME Journal of Electronic Packaging (JEP). He once received Journal of Electronic Packaging Associate Editor of the Year Award. He is also a member of K-16 (K-16: Heat Transfer in Electronic Equipment). I served in ASME EPPD Technical Committee in 2009-2010. I also served as a liaison for over three years for SRC (Semiconductor Research Corporation) projects between the research institutions and participating companies and helped expedite research work and collaboration between them.

Bio Teng

ANNETTE TENG (SM: 2001)is the Chief Technology Officer at Promex Industries, a manufacturer of electronic and medical components in Silicon Valley, since 2014.  She has spent most of her career in electronic component packaging and manufacturing in both corporate and academic environments.  Born in Borneo (Malaysia), she left at 16 to attend Sweet Briar College in Virginia.  After Graduating from University of Virginia with a Ph.D. in Materials Science, she moved to Silicon Valley and started her career in the IC world at Signetics.  She has worked in components packaging and assembly at Philips Semiconductor, Linear Technology Corp. and Corwil Technology.  Prior to joining Promex, she was Package Assembly Manager at Silanna in Australia for 3 years.   She also worked at Hong Kong University of Science and Technology and helped launch their electronics packaging programs from 1997 to 2000.  She has published at ECTC and Meptec in the area of dicing, die attach films and package delamination.  She has been active in IEEE-EPS Chapter activities in Silicon Valley since 2000 and is currently the Chair of the IEEE-EPS Santa Clara Chapter.

Bio Poliks

MARK POLIKS (M: 2004) is Empire Innovation Professor of Engineering, Professor of Systems Science and Industrial Engineering, Professor of Materials Science and Engineering and Director of the Center for Advanced Microelectronics Manufacturing (CAMM) at the State University of New York at Binghamton.  In 2006 he established the first research center (CAMM), to explore the application of roll-to-roll processing methods to flexible electronics and displays, with equipment funding from the United States Display Consortium (USDC) and the Army Research Lab.  His research is in the areas of industry relevant topics that include: high performance electronics packaging, flexible hybrid electronics, medical and industrial sensors, materials, processing, aerosol jet printing, roll-to-roll manufacturing, in-line quality control and reliability.  He has received more than $20M in research funding from Federal, New York State and corporate sources and more than $30M in equipment funding from federal and state sources.  He is the recipient of the SUNY Chancellor’s Award for Excellence in Research.  He leads the New York State Node of the DoD NextFlex Manufacturing USA and was named a 2017 NextFlex Fellow.  He has authored more than one-hundred technical papers and holds forty-six US patents.  Previously he held senior technical management positions at IBM Microelectronics and Endicott Interconnect.  Poliks is a member of technical councils for the FlexTech Alliance, NBMC and NextFlex, and on the NextFlex Governing Council.  He is an active member of the IEEE Electronics Packaging Society Electronic Component and Technology Conference and served and the 69th ECTC General Chair.   Poliks received dual undergraduate degrees, with honors, in chemistry and mathematics from the University of Massachusetts and a Ph.D. from the University of Connecticut in materials science and engineering.  He was a McDonnell-Douglas post-doctoral fellow working on solid-state magnetic resonance at Washington University, St. Louis before starting his career at IBM.

McCluskey Bio

PATRICK MCCLUSKEY (M: 1985, SM: 2015) (B.S.(’84) Lafayette College; M.S.(’86) and Ph.D. (’91), Materials Science and Engineering, Lehigh University) is a Professor of Mechanical Engineering at the University of Maryland, College Park and the Mechanical Engineering Department’s Division Leader for Electronic Products and Systems.  He has over 25 years of research experience in the areas of thermal management, reliability, and packaging of electronic systems for use in extreme temperature environments and power applications.  Dr. McCluskey has published three books and over 125 peer-reviewed technical articles with over 2000 citations, including over 40 articles in IEEE journals and major EPS conferences, such as ECTC and iTHERM.  He has also served as technical program or general chair of IEEE conferences on high temperature electronics and integrated power electronic packaging, as well as being the organizer of the President’s panel session on Power Module Integration at ECTC 2016, and panel sessions at ITHERM and ITEC.  Dr. McCluskey has provided a short course on integrated thermal packaging of power electronics at ECTC and iTHERM since 2013, along with short courses at IWIPP and 3D-PEIM.  He is an associate editor of the IEEE Transactions on Components, Packaging, and Manufacturing Technology, and of Microelectronics Reliability.  He is a senior member of IEEE and the chair of the EPS Technical Committee on Energy and Power Electronics.  He has also served as IEEE EPS representative to the Future Car Workshop.  He is a fellow of IMAPS and a member of ASME and TMS/AIME.

M Farooq

Mukta Farooq (M’10-SM’12-F’16) Dr. Mukta Farooq is an IBM Distinguished Research Scientist, IBM Lifetime Master Inventor with 232 granted US Patents, and a member of the IBM Academy of Technology. She is an IEEE Fellow, and a Distinguished Alumna of IIT Bombay. She is currently the Heterogeneous Integration Technology Leader at IBM Research, working on 2 nm CMOS 3D TSV integration and fine pitch die-stacking for AI Computing.

Her expertise includes semiconductor materials and structures, Heterogeneous Integration, 3-Dimensional (3D) Integration, flip-chip and die stacking technology, lead-free alloys, C4, Cu hybrid bonding, micropillar, ball / column grid arrays, chip package interaction, CMOS FET BEOL (Back End of Line) processing, packaging technology, and intellectual property development. She was awarded an Outstanding Technical Achievement Award for her pioneering and sustained contributions to IBM’s 3D Technology.

She has several patents designated as high value because of their use in semiconductor manufacturing. Her patents and intellectual property contributions are in multiple areas of semiconductors and microelectronics packaging: (1) Lead-free alloys and structures for C4, Ball Grid and Column Grid Arrays (2) Crackstop and chip package interaction improvement structures and processes (3) High BEOL TSV integration and evaluation (4) TSV proximity effect mitigation structures (5) Wafer level bonding structures to enable tight die-die coupling (6) Bond and assembly (7) Capillary underfills (8) Heterogeneous Integration structures including surface bridges, die-stacking, wafer level processing (9) Architectures enabling AI compute. Key portions of this IP and know-how have been used in IBM mainframes and in several products such as the Hybrid Memory Cube [© Micron Technology] logic controller. Some of this IP is planned to be deployed in future generations of IBM AI Units.

Mukta has contributed technology papers to major conferences [such as ECTC 2022, IRPS 2015, IEDM 2011], given invited talks/papers [iMAPS, IRPS, others], and taught short courses at key technical conferences [3D Integration courses at IEDM, EDTM, SEMICON West, and the SOI-3D-Sub Vt conference].

Mukta is the Founding Member and current Chair of the EPS Mid-Hudson Valley Chapter that has membership along the Hudson Valley area, from Albany to Yorktown Heights, New York. She has organized with other volunteers several lectures and mini symposia in advanced packaging technology. She is also on the EPS Fellows Evaluation Committee [2023 and 2024]. She is an IEEE EDS Distinguished Lecturer and an invited lecturer to Women in EDS. Mukta has previously served 2 terms [3 years each] as an elected Member at Large of the Electron Device Society Board of Governor, and has actively supported EDS for the last 15 years, including as Chair of the EDS Mid Hudson Chapter. Mukta was awarded the 2022 IEEE EPS award for sustained lifetime contributions to electronic packaging. In 2021, she received the IEEE Region 1 Technological Innovation Award. She is active in mentoring professionals in engineering & technology.

Mukta holds a Ph.D. in Materials Science & Engineering from Rensselaer Polytechnic Institute, an M.S. in Materials Science from Northwestern University, and a B.Tech [Technology] in Metallurgical Engineering from the Indian Institute of Technology, Bombay.

Bio Shaw Fong Wong

Shaw Fong Wong (M ’07, SM ’11) is currently the Probe Card Module Department Director in one of the Kulim Campus’ factories. He joined Intel Technology, Malaysia as the ATD-Malaysia Q&R Engineer back to Y2001. Over the years, he assumed different positions and portfolios related to packaging process, assembly, test and material technology developments. During his tenure, Shaw Fong supported multiple chipset development programs specialized in warpage and SJR testing development. He later harness competencies related to packaging process, assembly, test and material technology developments. In 2009, he was promoted to manage the ATTD-Malaysia Core Competency Laboratory and led a team of lab engineers and technicians working on mechanical and structural testing in supporting various package platform developments, virtual factory support and customer/industry engagements. His engagement spread across APAC factories and dealing with standard transfer, direct startup of product level warpage characterization. He played significant role in dealing with coplanarity and warpage related review boards to ensure the right fixes are in place. Shaw Fong received his Bachelor and Master’s Degree in Mechanical Engineering from National University of Malaysia (UKM) and Science University of Malaysia (USM) respectively. Lately, Shaw Fong also obtained a PhD degree from University of Kuala Lumpur (UniKL) in electronic packaging research. Shaw Fong has total of 8 patent fillings and Intel Trade Secrets and published more than 70 articles both in internal and external conference or technical journals. In his personal capacity, Shaw Fong has held multiple roles in IEEE/EPS organization, chairing many local or regional IEEE/EPS conferences in Malaysia and had been served as IEEE/EPS Malaysia Chapter chair since Y2016. He was nominated to receive the Outstanding Young Engineer Award and Region-10 Contribution Awards in 2010 and 2019 respectively by IEEE/EPS society too. Shaw Fong’s is very much into sports especially football (soccer) of which his favorite team is Liverpool and he is a strong believer in: You Never Walk Alone!

Bio Przemek Gromoala

PRZEMYSLAW GROMALA (M ’14, SM ‘20) is a senior simulation expert at Robert Bosch GmbH, Automotive Electronics in Reutlingen, Germany. He currently leads an international simulation team and an FEM validation and verification laboratory, focusing on the implementation of simulation design of electronic control modules and multi-chip power systems for hybrid drives. His technical expertise includes materials characterization and modeling, multi-domain and multi-scale simulation including fracture mechanics, V&V techniques, and prognostics and health management of safety-relevant electronic control systems. Established an extensive international network within Robert Bosch GmbH (AE and other business units) and between top universities (TU Delft, TU Chemnitz, University of Maryland, Auburn University, IISC Bangalore) and R&D institutes (FhG ENAS, IMEC, RE.SE) in Europe and worldwide (USA, China, India). He established direct contacts between Bosch and semiconductor industry leaders: e.g., Intel, Xilinx. Infineon, On-Semi.

Before joining Bosch, Mr. Gromala worked at Delphi (now Aptiv), at the European Development Center in Krakow, Poland, and at the Infineon R&D Center in Dresden, Germany.

He holds a PhD in mechanical engineering from the Cracow University of Technology.

Przemyslaw Gromala is an active member of IEEE EPS conference committees:

– ECTC (TMSC co-chair 2017/18, TMSC chair 2018/19 and 19/20),

– EuroSimE (since 2016, various roles),

– REPP symposium – committee member and European liaison (2020 and 2021)

– iTherm (Mechanics and Reliability co-chair 2019 and 2020, Mechanics and Reliability track chair 2021 and 2022, Panel co-chair 2021 and 2022)

– ASME: InterPACK (Automotive tract co-chair 2017, Automotive track chair 2018, -19, technical program co-chair 2020, technical program chair 2021, General conference chair 2022).

– He is a chair of the IEEE EPS TWG Reliability since 2022, before he was a co-chair for 2 years.

Przemyslaw Gromala contributes to the IEEE EPS community by presenting his work at many conferences and professional development courses (EuroSimE, ECTC/iTherm). He has served/organized panels at many of these events (IEEE iTherm, ECTC, EuroSimE), on a variety of topics including materials characterization, numerical modeling, and prognostics and health management of electronics used in harsh environments.

He actively contributes to the IEEE EPS Heterogenous Integration Roadmap in three chapters:

– Automotive

– Simulation and Co-Design

– Reliability (as of 2021)

In addition to his IEEE activities, he is a member of the EPoSS (Chair of the EPoSS ID 2019 document, Quality, Reliability and Safety chapter) and ECS (Chair of the ECS SRIA 2020 chapter, Quality, Reliability, Security and Cyber Security chapter) committees – defining R&D and innovation needs as well as policy requirements related to the integration of smart systems and integrated micro- and nanosystems in Europe.

Przemyslaw Gromala is author and co-author of more than 50 papers in journals and conferences and two book chapters.

Bio Bock

KARLHEINZ BOCK (M’96)since 2014 has served as Professor and chair of electronics packaging and director of the institute of electronics packaging (IAVT) at the TU Dresden. Since 2008 he has served as a Professor of Polytronic Microsystems at the faculty of Communication and Electronics Engineering at the University of Berlin.  He earned his Diploma on electrical and communication engineering from the University of Saarbrücken, Germany in 1986 and his Dr.-Ing. (Ph.D.) for RF microelectronics from the University of Darmstadt, Darmstadt, Germany in 1994. From 1996 to 1999 he worked in the materials packaging and reliability department of IMEC vzw. in Leuven Belgium. He received the “Japan Society for Promotion of Science (JSPS) Award” in 1994 for his PhD thesis and worked as post-doc from 1994 to 1995 at the Tohoku University in Sendai, Japan.  He received two Doctor honoris causa, in 2012 from the Polytechnical University of Bukarest in Romania for his work on organic and flexible electronics and heterointegration and in 2019 from the Sikorsky-Polytechnical University of Kiew, Ukraine for his work in electronics packaging. Since 2017 he serves as a vice dean and since 2021 he serves as the dean of the faculty of electronics engineering and information sciences at the TU Dresden as well as in the rector of the TU Dresdens advisory boards for research and managing diversity as well as in the TU Dresden commission for environmental sustainability.

He served in the Fraunhofer Gesellschaft, from 2001 until 2014 where he has been employed as head of the Polytronic and Multifunctional Systems department at the Fraunhofer Institute for Reliability and Microintegration (IZM, Munich branch, from 2010 named EMFT) and as deputy director from 2006 until 2010 of IZM and from 2010 until 2012 as  acting director of Fraunhofer EMFT.

Karlheinz Bock has contributed more than 300 publications and more than 20 patents. He co-authored 16 best paper awards. (see Google Scholar and Research Gate) He is engaged in developing the technological community of 3D systems, heterosystem integration and packaging and organic and flexible electronics, advanced packaging and reliability. He serves on the emerging technology TPC of IEEE ECTC since 2008, as sub-committee member and vice chair 2011 and chair 2012; as member of IEEE IEDM since 2008 on TPC for display sensors MEMS (DSM) and as chair of DSM TPC in 2010; as the European arrangements co-chair 2011, chair 2012 of IEEE IEDM executive committee; furthermore he served on the IEEE ESTC conference technical program committee since 2012; 2016 he has served as the program chair of  IEEE ESTC 2016 and as the general chair of IEEE ESTC 2018. Since 2015-2018 he served as vice chair and from 2018-2020 as chair of the technical committee of emerging technologies of the IEEE EPS. Since 2020 he serves on the IEEE EPS ECTC executive committee and as a program chair of IEEE ECTC 2022 and at present as the vice general chair of ECTC2023. Since 2014-2018 and re-elected from 2020 he serves on the board of governors BoG of IEEE EPS for region 8.

Bio Schutt-Aine

JOSE SCHUTT-AINE (M 82-86, StM 86-88, M 88-98, SM ’98, F’07) received his B.S. degree in electrical engineering from the Massachusetts Institute of Technology, Cambridge, in 1981, and the M.S. and Ph.D. degrees from the University of Illinois at Urbana-Champaign (UIUC), Urbana, in 1984 and 1988, respectively. He joined the Hewlett-Packard Technology Center, Santa Rosa, CA, as an Application Engineer, where he was involved in research on microwave transistors and high-frequency circuits. In 1983, he joined UIUC, and then joined the Electrical and Computer Engineering Department as a member of the Electromagnetics and Coordinated Science Laboratories, where he is currently involved in research on signal integrity for high-speed digital and high-frequency applications. He is a consultant for several corporations. His current research interests include the study of signal integrity and the generation of computer-aided design tools for high-speed digital systems. Dr. Schutt-Ainé was a recipient of several research awards, including the 1991 National Science Foundation (NSF) MRI Award, the National Aeronautics and Space Administration Faculty Award for Research in 1992, the NSF MCAA Award in 1996, and the UIUC-National Center for Superconducting Applications Faculty Fellow Award in 2000. He is an IEEE Fellow, EPS Distinguished Lecturer, and served as Co-Editor-in-Chief of the IEEE Transactions on Components, Packaging and Manufacturing Technology (T-CPMT) from 2007 to 2018.

Bio Nguyen

Luu Nguyen (AM ’92, M ’96, SM ’99, F ’01) is the Director of Quality and Reliability at PsiQuantum since 2019, a start-up based in Palo Alto, CA, that aims at building the first large-scale, error-corrected, general-purpose silicon photonics-based quantum computer.  I drive the quality and reliability efforts around integrating a complex quantum optical system-on-a-chip, based on scalable foundry manufacturing processes.  As an integrated system, the technical challenges span control systems, cryogenics, optical design, non-linear quantum optics, optoelectronic packaging, process development, software, test and measurement, and supply chain and logistics.  I co-lead IEEE Quantum, an IEEE Future Directions initiative launched to serve as IEEE’s leading community for all projects and activities on quantum technologies.  A project plan was developed

to address the current landscape of quantum technologies, identify challenges and opportunities, leverage and collaborate with existing initiatives, and engage the quantum community at large.  I serve on the Steering Committee for IEEE Quantum Week, the flagship conference on all quantum computing and engineering topics, and participate in many technical committees (ECTC Packaging Technologies, TC on Reliability, TC on Emerging Technologies, Rel. for Electronics & Photonics Packaging Symposium), award committees (CPMT Field Award, SMTA Society Awards, and ASME Allan Kraus Thermal Management Award, EPPD Awards), and EPS Fellows Nomination committee.  I am currently an Associate Editor for T-CPMT, and have been a Guest Editor for three past issues (Drop Testing (2007), Wafer Level Packaging (2008, 2009).)

I retired as a Fellow at Texas Instruments in 2019, where I worked on various strategic initiatives that included sensors, printed electronics, high voltage packaging, wafer-level packaging, thermal management, design-for-manufacturability, and design-for-reliability.  I graduated with a Ph.D. in Mechanical Engineering from MIT and worked at IBM Research, Philips Research, and National Semiconductor.  I have co-edited two books on packaging technologies.  I have written several book chapters, have over 70 patents and invention disclosures, and over 200 publications.  I am a Fellow of IEEE and ASME, a Fulbright Scholar (Finland 2002), a Fannie and John Hertz Fellow, and an AAAS Mass Media Science and Engineering Fellow.  I received two Best Paper of Conference Awards, one Best Poster of Conference Award, and eight IMAPS and IEMT Best Session of Conference Awards.  I have received the 2004 IEEE CPMT Outstanding Sustained Technical Contributions Award, the 2015 IEEE Outstanding Engineering Manager Award for the IEEE Region 6, and the 2018 Surface Mount Technology Association Member of Technical Distinction.  Other awards also include the 2003, 2014, 2015, and 2016 Mahboob Khan Outstanding Mentor Award from the Semiconductor Research Corporation to recognize contributions to student mentoring, research collaboration, and technology transfer.  I co-led the efforts at National Semiconductor to garner the Electronic Product Design (UK) e-Legacy “Investment in Training Award” (2007), the “Investment in Education Award” (2007), and the European Electronics Industry “Investing in People” Elektra Award (2006) for the most innovative company training scheme to foster professional development, practical training, best practices sharing, mentoring, cross-training, and e-learning among more than 2,500 engineers worldwide.

Bio Bailey

CHRIS BAILEY (A’01, M’03, SM’05) I am a tenured professor at Arizona State University, Tempe, Arizona.  Prior, I was Professor of Computational Mechanics and Reliability at the University of Greenwich, London, United Kingdom. I received my PhD in Computational Modelling from Thames Polytechnic in 1988, and an MBA in Technology Management from the Open University in 1996. Before joining Greenwich in 1991, I worked for three years at Carnegie Mellon University (USA) as a research fellow in materials engineering.

One of my main achievements with regards to CPMT was helping to establish the Region 8 flagship conference ESTC (Electronics System-integration Technology Conference). I was the Programme Chair for the first conference held in Dresden, and was the General Chair for the 2008 conference in London. In 2007 I was the local chair for the IEEE EPS sponsored EuroSime conference held in London, and since 2009 have worked with the EuroSime team as co-editor of the proceedings and track chair for multi-physics modelling.

Since 2010 I have had the pleasure of serving you as a member of the CPMT Board of Governors. During my first term on the BoG I also took on the role of Strategic Director for Student Programs with the aim of supporting students involved in CPMT activities worldwide. Particular achievements include arranging financial support for student attendees at the International Spring Seminar on Electronics Technology (ISSE) as well as promoting student membership at events such as ECTC, EPTC and ESTC.
Other CPMT activities that I have been involved with include membership of technical committees for EPTC (Singapore), Eurosime (Europe), ISSE (Europe) and ICEP/HDP (China) where I am a regular attendee and presenter. I have also worked closely with others in Europe to help promote closer co-operation between CPMT and IMAPS for the benefit of the whole community.

My research has resulted in over 250 publications. I am currently an Associate Editor for the CPMT Transactions and have been a guest editor on the journal of Soldering and Surface Mount Technology. I am also a committee member of the Innovative Electronics Manufacturing Research Centre (IeMRC) in the UK and have participated in a number of UK Government sponsored overseas missions to promote collaboration and review electronic packaging technologies. Recently I became a member of the working group writing a new IEEE standard for Prognostics and Health Management for Electronic Systems.

Bio Pearsall

KITTY PEARSALL (AM’84-M’01-SM’02) received the BS degree in Metallurgical Engineering (1971) from the UT El Paso. Kitty received the MS and Ph.D. degree in Mechanical Engineering and Materials from the UT Austin in 1979 and 1983 respectively. Kitty worked for IBM from 1972 to 2013. In 2005 Kitty was appointed an IBM Distinguished Engineer and was elected to the IBM Academy of Technology. Kitty was a process consultant and subject matter expert working on strategic initiatives impacting component qualification and end quality of procured commodities. She engaged with worldwide teams implementing cross-brand, cross commodity processes/products that delivered high quality/high reliability end product.

Kitty received 4 IBM Outstanding Technical Achievement Awards; holds 9 US patents; 2 patents pending; and 8 published disclosures. She has numerous internal publications as well as 22 external publications in her field. Kitty is a licensed Professional Engineer (Texas since 1993). Kitty was the recipient of the UT Austin – Cockrell Engineering Distinguished Engineering Graduate Award in 2007 followed by induction into the UT Mechanical Engineering Dept. Academy of Distinguished Alumni in 2008. Kitty was awarded the Women in Technology Fran E. Allan Mentoring Award (2006) in recognition of her people development both in and outside of IBM. Currently Kitty is President of Boss Precision Inc. and works as an Independent consultant. This has included a one year engagement with Shainin Corporation.

Kitty is an active member in IEEE and CPMT. She is a member of TMS, American Society of Metals, and WIE. Kitty has more than 22 years’ experience with ECTC serving as a member of the ECTC Manufacturing Technology Committee (1993-2013) and as the Professional Development Course Chair since 2006. During Kitty’s 10 years on the CPMT Board of Governors she has served in many roles: Member at Large, Strategic Awards Director, VP of Education and currently Director of Chapter Programs. In each role Kitty made key contributions.

Kitty introduced the Regional Contribution Awards. She established the baseline for the CPMT Distinguished Lecturer’s (DLs) Program. The history of the DLs presentations to Universities, Research Centers, Conferences and CPMT Chapters was charted to determine if the program was meeting its founding principal; i.e., primarily supporting the CPMT chapters. Review of the data noted that this was not the case. Therefore Kitty focused on increasing Chapter usage which did improve over time. DL Budget tracking of planned versus actuals was initiated. Lastly, Kitty documented the roles and responsibilities of the VP Education and passed these on to the new VP. As Director of Chapter Programs Kitty is focusing on worldwide Chapter Communication as well as ensuring Chapters know their benefits and how to access them. First deliverable was a Worldwide Chapter Communication Survey highlighting best practices amongst them.

Bio Mattila

TONI MATTILA (M’08) is a research scientist and docent at Aalto University in Helsinki, Finland where he leads a research team that focuses on the reliability of electronic devices. He received his Ph.D. degree in electrical engineering in 2005 and an M.Sc. degree in materials science and engineering in 1999 from the Helsinki University of Technology (HUT). Since 1996, he has been working with electronics production technologies and reliability of electronic devices both in industrial and academic settings. Before joining HUT in 1999 he worked in Tellabs and Nokia.

Toni’s research has focused on electronics production technologies, soldering in electronics, failure mechanisms of electronic assemblies, MEMS technologies, and the development of improved methods for reliability assessment and lifetime prediction. Within the framework of his research Toni has been working in close co-operation with international electronics industry, research institutions and universities. His research has so far resulted in over fifty publications in scientific and technical journals and conferences. In addition, Toni has authored seven book chapters, held several professional tutorials during conferences and been a frequent speaker at conferences, seminars and technology fairs. He is also a frequent reviewer in several scientific journals, including CPMT Transactions.

Since 2008, Toni has been Chairman of the CPMT Finland Chapter. During this time he has, together with other board members, developed and revitalized local activities. More than 100 people attend seminars and events organized by the CPMT Finland chapter annually.  He has also established firm connections between the CPMT chapters in Scandinavia. Toni is currently an elected member of the Board of Governors of the CPMT.

Toni also works actively in the IEEE Finland Section, where he has been a member of the executive committee since 2008, and served in various positions. Other IEEE activities include, for example, a membership of technical committees for all three Electronics System Integration Technology Conferences (ESTC). In the past he has also acted in several other positions of trust. For example, he has been the chairman of a housing association for ten years.

Bio_Huffman

ALAN HUFFMAN (M: 2005, SM: 2007) is currently the Business Unit Director for Heterogeneous Integration at SkyWater Technologies where he is responsible for business development, customer engagement.  Prior, he was the Director of Engineering for Micross Advanced Interconnect Technology in Research Triangle Park, NC.  He received the B.S degree in physics from The University of North Carolina at Chapel Hill in 1994. From 1994 to 2005 he was a Member of the Technical Staff at MCNC Research & Development Institute working on development and implementation of wafer level packaging technologies, reliability and failure mode analysis of flip chip devices, and optoelectronic and MEMS packaging.  In 2005 he joined RTI International and was a Senior Research Engineer and Program Manager for WLP technology with RTI’s Electronics and Applied Physics Division.

Over the course of his career, his focus has been on the development and implementation of advanced interconnect technologies, including wafer level packaging, flip chip and micro-bump interconnect, 2.5D and 3D integration, and characterization and process development for electronic materials used in these technologies.  He has authored or co-authored numerous papers and presentations on a number of advanced packaging topics, particularly on high density interconnect technologies and characterization of polymer material processes.  He was awarded an RTI President’s Award in 2012 for his contributions to the 3D microsystems program and received 6 Highly Published Author awards during his tenure with RTI International.

Alan has been an active member of IEEE EPS for over a decade, joining CPMT in 2005 and was elevated to Senior Member in 2007.  In 2005 he joined the Interconnections technical subcommittee for the Electronic Components and Technology Conference (ECTC) where he served for 8 years.  He has been a member of the ECTC Executive Committee since 2011, served as the ECTC General Chair in 2016, and is currently the ECTC Exhibits Chair.  He joined the CMPT Board of Governors in 2016 as a Member at Large.  He is currently the Vice President, Membership for EPS.

Bio Perfecto

ERIC PERFECTO (M’95, SM’01, F’17) has extensive experience working in microelectronics. At IBM, Eric has led the development of multi-level Cu-polyimide advanced packages for high-end systems, followed by the introduction of Pb-free solder interconnects and 2.5D wafer finishing. As part of the IBM Microelectronics Division divestiture, Eric moved to GLOBALFOUNDRIES where he established a Si Photonics packaging development line. In 2019 he returned to IBM part time to establish a heterogeneous integration line in Albany. He holds a M.S. in Chemical Engineering from the University of Illinois and a M.S. in Operations Research from Union College.

An author of more than 80 technical papers and three book chapters, Eric received two Best Conference Paper Awards (2006 ESTC and 2008 ICEPT-HDP) and the 1994 Prize Paper Award from CPMT Trans. on Adv. Packaging. He holds 55 US patents and has been honored with two IBM Outstanding Technical Achievement Awards.

Eric served as the 57th ECTC General Chair, the 55th ECTC Program Chair and is the current ECTC Publicity chair. For the last 12 years, Eric’s popular Flip Chip Fabrication and Interconnection course has been given at ECTC to great reviews. He is an EPS Distinguish Lecturer, an IEEE Fellow, and has achieved IMAPS and SPE senior membership. 

Eric has represented the EPS members previously, elected 4 times to the BoG. For 3 years he served as the EPS Strategic Director of Global Chapters and Membership where he focused on enhancing the EPS membership value.  Through his efforts, the CPMT Transactions are now part of the EPS membership. For 8 years, he was the EPS Awards Program Director responsible for the EPS Mayor Awards, the Regional Awards, the PhD Fellowship, the ECTC Student Travel Awards and the ECTC Volunteer Award.  Currently, he chairs the EPS Field Award committee. At a local level, Eric is the membership Chair of the Mid-Hudson IEEE Section and founding member of the EPS Mid-Hudson EPS Chapter where he serves as membership chair.

Bio Mahajan

RAVI MAHAJAN is an Intel Fellow responsible for exploring and developing innovative technologies for assembling and packaging semiconductor components, with a particular emphasis on future generations of semiconductor manufacturing technology. Ravi also represents Intel in academia through research advisory boards, conference leadership and participation in various student initiatives. For over three decades he has led efforts to define and set strategic direction for package architecture, technologies, and assembly processes for multiple iterations of Intel packaging and assembly architectures and processes. Dr. Mahajan joined Intel in 1992 after earning Ph.D. in Mechanical Engineering from Lehigh University.

A prolific inventor and recognized expert in microelectronics packaging technologies, Mahajan is an inventor on 151 patent families, and these 151 patent families have led a total of 450 patents and applications. This includes the original patent for a silicon bridge that became the foundation for Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) technology currently deployed in high volume manufacturing for semiconductor devices and graphics parts. His early insights also led to high-performance, cost-effective cooling solutions for high-end microprocessors and the proliferation of photo-mechanics techniques used for thermo-mechanical stress model validation. Ravi has written several book chapters and more than 50 papers on topics related to his area of expertise.  He has delivered numerous plenary addresses and invited talks all over the world.  He is also one of the leaders of the IEEE-SEMI-ASME driven Heterogeneous Integration Roadmap (HIR) effort that today underpins R&D efforts in packaging across multiple geographies.

His contributions during his Intel career have earned him numerous industry honors, including the SRC’s 2015 Mahboob Khan Outstanding Industry Liaison Award, the 2016 THERMI Award from SEMITHERM, the 2016 Allan Kraus Thermal Management Medal & the 2018 InterPACK Achievement award from ASME, the 2019 “Outstanding Service and Leadership to the IEEE” Awards from IEEE Phoenix Section & Region 6 and more recently the 2020 Richard Chu ITherm Award and the 2020 ASME EPPD Excellence in Mechanics Award. He is one of the founding editors for the Intel Assembly and Test Technology Journal (IATTJ) and currently VP of Publications & Managing Editor-in-Chief of the IEEE Transactions of the CPMT. He has long been associated with ASME’s InterPACK conference and was Conference Co-Chair of the 2017 Conference. Ravi is a Fellow of two leading societies, ASME and IEEE.  He was elected to the National Academy of Engineering in 2022 for contributions to advanced microelectronics packaging architectures and their thermal management.

Bio Braun

TANJA BRAUN (AM: 2002; M: 2003; SM: 2017) studied mechanical engineering at Technical University of Berlin with a focus on polymers and micro systems and joined Fraunhofer IZM in 1999. In 2013 she received her Dr. degree from the Technical University of Berlin for the work focusing on humidity diffusion through particle-filled epoxy resins. Tanja Braun is head of the group Assembly & Encapsulation Technologies. Recent research is focused on fan-out wafer and panel level packaging technologies and Tanja Braun is leading the Fan-out Panel Level Packaging Consortium at Fraunhofer IZM Berlin.

Results of her research concerning packaging for advanced packages have been presented at multiple international conferences. Tanja Braun holds also several patents in the field of advanced packaging.

In 2014 she received the Fraunhofer IZM research award and in 2021 the Exceptional Technical Achievement Award from IEEE Electronics Packaging Society (EPS) and the IMAPS Sidney J. Stein Award.

Tanja Braun is an active member of IEEE. She is member of the IEEE EPS Board of Governor (BOG) and Technical Chapter “Materials & Processing” as well as the IEEE EPS Region 8 Program Director.

Bio McCann

DAVID MCCANN (M’89) is the VP of Technology for the Electronics Packaging Society.  David was a member of the ECTC Executive Committee for 10 years and later participated on the ECTC Steering Committee for two years.

David is currently Sr. VP, Chief of Staff, Business Unit at Amkor Technology in Tempe, AZ.  Prior to this role, he was at Rockley Photonics in Pasadena, CA for three years where he led packaging development for medical sensors and communications transceivers.  Prior to Rockley Photonics, David was at GlobalFoundries for eight years where he was Vice President of Post Fab Development and Operations.   He was responsible for GlobalFoundries internal bump and probe factories, for packaging and test development for Global’s Foundry, ASIC, and RF businesses, for OSAT partnerships, supply chain qualification and external bump-probe-assembly-test production.  He led the Post Fab process and business integration between GlobalFoundries and IBM, and later was part of the team that transitioned the ASIC business to Marvell.  He was based in Malta, New York.

Prior to GlobalFoundries, David was at Amkor Technology for 11 years leading flip chip technology development and the flip chip business unit.  Amkor is a leading OSAT (Outsourced Assembly and Test) company, with factories across Asia.  His technology and business focus was primarily on HPC, mobile, MEMS, and gaming packaging.

Prior to Amkor, David was at Biotronik GmbH, a pacemaker and implanted defibrillator supplier for 10 years, in product development, process development, and operations leadership roles.

Jeffrey C. Suhling

JEFFREY C. SUHLING (A’94, M’01)Jeffrey C. Suhling received his Ph.D. degree in Engineering Mechanics in 1985 from the University of Wisconsin. He then joined the Department of Mechanical Engineering at Auburn University, where he currently holds the rank of Quina Distinguished Professor and Department Chair. From 2002-2008, he served as Center Director for the NSF Center for Advanced Vehicle Electronics. He was appointed Department Chair of the Department of Mechanical Engineering in 2008.

His research interests include solid mechanics, stress and strain analysis, material characterization, experimental mechanics, advanced and composite materials, finite element analysis and computational mechanics. He works primarily on applications of these fields to electronics packaging, including silicon sensors for stress and temperature measurement, and materials characterization and constitutive modeling of microelectronic solders and encapsulants. Dr. Suhling has authored or co-authored over 600 technical publications, and he has advised over 100 graduate students at Auburn University. He is a Fellow of ASME, and is a member of IEEE, SMTA, IMAPS, SEM, ASTM, and TAPPI.

In ASME, Dr. Suhling served as Chair of the Electrical and Electronic Packaging Division during 2002-2003, and was on the EPPD Executive Committee from 1998- 2003. Dr. Suhling was the Technical Program Chair of the ASME InterPACK ‘07 Conference, and General Chair of the ASME InterPACK ‘09 Conference. He also served the InterPACK Conference Series as Finance Chair (2003), Track Chair for Modeling and Characterization (1999), Track Chair for Reliability (2005), and Honors and Awards Chair (2011). He was Associate Editor of the ASME Journal of Electronic Packaging from 2014-2019.

In IEEE, Dr. Suhling has been a member of the Electronics Packaging Society (formerly CPMT Society) for the past 30 years. He has served on the ECTC Program Committee (Applied Reliability) from 2003-present, and as Co-Chair of the ECTC Professional Development Course Committee from 2007-present. He was first elected to the IEEE Electronics Packaging Society Board of Governors in 2014, and has served as Member at Large (2014-2016), Director of Membership Services (2016-2018), and Vice President, Education (2019-present). Dr. Suhling has served in several roles in the ITherm Conference Series including Conference Program Vice Chair (2017), Conference Program Chair (2018), and Conference General Chair (2019). He is currently serving as Chair of the ITherm PDC Committee, and Co-Chair of the ITherm Best Paper Committee.

Bio Thompson

PATRICK THOMPSON (M’87, SM’92) earned his BS, MS and PhD degrees in Chemical Engineering at the University of Missouri-Rolla. He has more than 35 years of experience  in advanced packaging research, development and transfer to manufacturing, contributing to  technologies ranging from flip chip fabrication and packaging, flip chip on board and chip scale packages, to multi-chip packaging, MEMS, optoelectronic packaging, and high performance portable packaging. He has led teams at Bell Labs, AMI Semiconductors , and Motorola (now Freescale). Since 2001, he has been a Senior Member of the Technical Staff at Texas Instruments, where he currently leads wafer-based packaging technology development.

Pat is active in industry-consortia and industry-university partnerships, including mentoring SRC custom projects and PhD students.

Pat has 15 patents and over two dozen publications. He has presented packaging tutorials and given invited talks at leading packaging conferences. He is a member of the Electronic Components and Packaging Technology Conference technical program committee, where he has held multiple positions, including General Chair of the 2006 ECTC, and is now the Financial Chair. He has served at both the local and Society level of the EPS holding positions including Member-at-Large of the Board of Governors, Administrative Vice President, and Technical Vice President of the EPS.