d ?= dx or d ?= du - Both are always FALSE.

[JimLewis]

In https://github.com/VUnit/vunit/blob/master/examples/vhdl/array_axis_vcs/src/fifo.vhd#L44
assert always (not rst and wr -> not (d ?= dx or d ?= du))@rising_edge(clkw)
report "wrote X|U to FIFO";

With "?=" when one operand is an 'X' or a 'U' it only returns '1' when the other value is a '-', otherwise, it returns 'X' or 'U'. Probably not what you want

I think you need a regular "="

[tmeissner]

I don't like or use these VHDL-08 operators anyway, as they aren't that transparent for me. Now I would write something like this:

assert always (not rst and wr ->  to_x01(or d) /= 'X')@rising_edge(clkw) report "wrote X|U to FIFO";