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asarkar8400/README.md

LinkedIn GitHub followers

I am focused on RTL Design Problems

  • B.E. in Electrical Engineering from Stony Brook University
  • Pursuing M.S. in Computer Engineering @ Stony Brook University
  • Discord: i schleep

Image

Image

Languages & Tools

SystemVerilog VHDL QuestaSim Xilinx Vivado Xilinx Vitis HLS Synopsys Design Compiler MATLAB CUDA Image Keras

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  1. CUDA_Matrix_Multiplication_GPU_Acceleration CUDA_Matrix_Multiplication_GPU_Acceleration Public

    Implemented matrix multiplication algorithms in CUDA including memory coalescing, shared memory caching, and 2D block tiling, achieving over 1000x speedup compared to the CPU implementation.

    Cuda 1

  2. SIMD_Multimedia_Processing_Unit SIMD_Multimedia_Processing_Unit Public

    Forked from dannydyl/SIMD_Multimedia_Processing_Unit

    This project involves the design and implementation of a 4-stage pipelined multimedia processing unit using VHDL/Verilog hardware description languages.

    VHDL 1

  3. DNN_Based_ADC_Calibration_Accelerator DNN_Based_ADC_Calibration_Accelerator Public

    Implementation of a lightweight quantizd DNN for calibration of the NSLS-II Electrometer ADC channels. Utilized hls4ml to convert the QKeras model to HLS and deployed onto a Xilinx Zynq-7020 FPGA

    Jupyter Notebook 1

  4. Pipelined_CSA_Virtuoso Pipelined_CSA_Virtuoso Public

    Designed a Pipelined 8-bit Carry Select Adder on the transistor level using Cadence Virtuoso

  5. SCD41_Sensor_Display_System SCD41_Sensor_Display_System Public

    Embedded C firmware using HAL-based abstractions for interfacing a Sensirion SCD41 sensor using an AVR128DB48 microcontroller and displaying the measured values on a SerLCD.

    C

  6. 2DConvolution_HardwareAccelerator 2DConvolution_HardwareAccelerator Public

    Implemented a parameterized hardware accelerator for 2D convolution with bias, pipelined MAC arrays in parallel, input memories, and output FIFOs with AXI-Stream interfaces.

    SystemVerilog