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edi0328/README.md

Hi, I'm Edison 👋

Welcome to my GitHub! I'm a Computer Engineering student at McGill University who enjoys building across software, computer systems, and signal processing.

What I'm interested in

  • Systems programming, operating systems, and computer architecture
  • Digital systems, microprocessors, and hardware/software interfaces
  • Algorithms, data structures, and software engineering
  • Signal processing, filtering methods, data analysis, and applied research
  • Python, C, Rust, MATLAB, VHDL, and JavaScript

Currently working on

  • A MATLAB-based statistical signal-processing pipeline for my capstone project, focused on filtering methods and research-driven implementation
  • Computer engineering projects involving RISC-V, VHDL, and low-level systems concepts
  • Improving my software engineering fundamentals through practical projects and clean documentation

Featured projects

  • RISCV_Pipeline — RISC-V pipelined processor project with hazard detection in VHDL
  • TuringPoker — Python project exploring game logic and programming fundamentals
  • zero2prod — Rust backend development practice

Thanks for visiting — feel free to explore my projects!

Pinned Loading

  1. RISCV_Pipeline RISCV_Pipeline Public

    Project for ECSE425 where we implement a RISC pipelined processor with hazard detection in VHDL.

    VHDL

  2. TuringPoker TuringPoker Public

    Python poker bot project for the McGill Poker Bot Tournament, focused on game logic and automated decision-making.

    Python 1

  3. zero2prod zero2prod Public

    Rust web backend practice project following Zero To Production, with CI, configuration, database migrations, and deployment-oriented structure.

    Rust