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cgen: skip empty asm amd64 {} blocks, to ease prototyping
1 parent 6be2fbb commit ccac075

3 files changed

Lines changed: 12 additions & 1 deletion

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‎vlib/v/gen/c/cgen.v‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3337,6 +3337,10 @@ fn (mut g Gen) gen_attrs(attrs []ast.Attr) {
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}
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fn (mut g Gen) asm_stmt(stmt ast.AsmStmt) {
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if stmt.templates.len == 0 && stmt.input.len == 0 && stmt.output.len == 0
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&& stmt.global_labels.len == 0 && !stmt.is_goto && !stmt.is_volatile {
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return
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}
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g.write('__asm__')
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if stmt.is_volatile {
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g.write(' volatile')

‎vlib/v/gen/c/text_manipulation.v‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ const trace_gen_wanted_value = $d('trace_gen_wanted_value', '')
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fn (mut g Gen) trace_gen_wanted_context(last_character_len int, s string) {
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last_n := g.out.last_n(last_character_len)
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eprintln('> trace_gen_wanted, last characters:\n${last_n}\n')
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eprintln('> trace_gen_wanted, found wanted cgen string `${trace_gen_wanted_value}` in generated string ${s}')
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eprintln("> trace_gen_wanted, found wanted cgen string `${trace_gen_wanted_value}` in generated string: \"${s}\"")
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print_backtrace()
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}
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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,7 @@
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fn test_empty_asm_statements() {
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asm amd64 {
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}
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asm arm64 {
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}
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assert true
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}

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