Verification and Computer Architecture on VCA: Verification and Computer Architecture

Porting XiangShan to the Xilinx U55C FPGA

Tue, 15 Apr 2025 13:03:42 +0200

I recently ported the XiangShan RISC-V CPU core to the Xilinx Alveo U55C FPGA. This post outlines the key steps, practical tips, and workarounds that go beyond the official documentation—especially helpful for those transitioning from ASIC/simulation workflows to FPGA-based development.

Getting Started with FPGAs

If you’re new to FPGAs (as I was), setting up a complete system can be confusing.

FPGA Basics

Unlike simulation or ASIC environments, FPGAs require you to manually generate external signals like clock and reset. These are mapped to physical pins via XDC constraint files, and you can find U55C-specific examples in Xilinx’s documentation. Board files also provide crucial clock configuration info.

Lean Profiling

Wed, 11 Sep 2024 00:00:00 +0000

Lean has good support for profiling tactic scripts, with incrementally more information. There are two different profilers in Lean, a general profiler called profiler and a newer profiler with more detailed information called trace.profiler.

`trace.profiler`

First we will cover the more advanced trace.profiler, which can give an incremental trace of the time taken for each tactic in the tactic script. For example, enabling the profiler using set_option trace.profiler true in will produce the profiling trace shown below.

Contact

Mon, 01 Jan 0001 00:00:00 +0000

Browse the directory.

Address

Verification and Computer Architecture Lab
EPFL IC IINFCOM VCA
BC 103 (Bâtiment BC)
Station 14
CH-1015 Lausanne

People

Mon, 01 Jan 0001 00:00:00 +0000

Projects

Mon, 01 Jan 0001 00:00:00 +0000

Our code and artefacts are available on GitHub. Here are some of our main projects that involve artifact code.

Graphiti

Formally verified graph rewriting for dataflow circuits. Graphiti uses the Lean theorem prover to verify that out-of-order execution transformations in dataflow circuits preserve program semantics. Published at ASPLOS ‘26.

Source code (Lean)

FSA — SystolicAttention

A hardware architecture that fuses FlashAttention within a single systolic array, eliminating off-chip memory traffic for attention computation. The design is implemented in Chisel/Scala with an FPGA prototype.