Zip CPU

@zipcpu

FPGA design engineer and blogger, placing particular emphasis on test and formal verification

Gisselquist Technology, LLC,

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Zip CPU
@zipcpu
Oct 4, 2018
Wow, lots of new twitter followers just joined. Welcome! Just to give you an opportunity to get to know me and the ZipCPU blog, here's a bit about me and what you can expect here: zipcpu.com/blog/2018/10/0… Again, welcome!
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Zip CPU
@zipcpu
Oct 13
I can't say I've never made this mistake before Note that TFR_WRITE != TFR_TXPARITY ... otherwise this might've worked accidentally ...
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Zip CPU
@zipcpu
Oct 1
This weeks design puzzle has been to build an AXI cache: AXI in, AXI out with all WSTRB bits set. I've been a bit surprised at the requirements of such a controller, and the more I've dug into it, the more challenging and complex it becomes.
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Zip CPU
@zipcpu
Sep 18
This stack exchange post has a good description of the problems with using AES-CTR for memory encryption. I love the included pictures. They tell the story well. crypto.stackexchange.com/questions/59/t…
Zip CPU
@zipcpu
Sep 17
Whoever thought AES-CTR could be used to secure memory ... is offering an expensive encryption that looks good but offers zero security.