A parallel regular expressions engine for LLVM IR that uses non-deterministic finite automaton (NFA). and LLVM Opcode as Symbol that match inputs in parallel on functions and instructions levels.
This project started with the question, Can't we replace the symbol in the finite automata transation with LLVM Opcode? 🤔
Running on large input file (Around 16k LoC).
- Install:
cargo install ir-regex
- Run:
ir-regex pattern file_path- Example: ir-regex "(add|sub)*" input.ll
Symbols
alloca,load,storeadd,sub,mul,sdiv,udiv,srem,uremfadd,fsub,fmul,fdiv,fneg,fremshl,ashr,lshricmp,fcmpor,and,xorcall,callbr,invokeselect,switch,gep,phisext,zext,Trunc,FPTruncbr,indirectbrresume,return,unreachable
Operators
- Choice:
| - Grouping:
(...) - Repetition:
*
Example:
(add|sub)*- Will match a sequence of add or sub instructions.
MIT License
Copyright (c) 2026 Amr Hesham
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
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The above copyright notice and this permission notice shall be included in all
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