Chinese memory giant CXMT is reportedly facing difficulties with HBM3 production, according to South Korean media. Late last month, it was revealed that CXMT had
begun risk production of HBM3E memory, lagging two generations behind Samsung, SK hynix, and Micron, who are already progressing with HBM4E sampling. At that time, it was known that the company was conducting HBM3E risk production in limited runs, but details were scarce. However, today we learn that three out of four HBM3E stacks are defective, indicating that CXMT currently operates at a 25% yield. Stacking DRAM is a complex task, as the technology required is much more intricate than planar DRAM manufacturing, an area where CXMT reportedly excels.
The low yields are reportedly due to the immaturity of the through-silicon via (TSV) technology that CXMT employs. In front-end manufacturing, CXMT achieves around 30% yields, while back-end processing yields about 70% on top of the original 30%. For instance, Samsung uses about 5,000 TSVs per layer on HBM2, and SK hynix uses more than 8,000 TSVs per layer on its HBM3. However, data suggests that CXMT is attempting to achieve HBM3E with only 3,000 TSVs per layer and is trying to pack 8 layers in the regular 8-Hi HBM3E configuration. Given these challenges, the company is unlikely to transition to a higher-capacity 12-Hi HBM in the near term as it addresses engineering challenges.