Zip CPU

@zipcpu

FPGA design engineer and blogger, placing particular emphasis on test and formal verification

Gisselquist Technology, LLC,

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Zip CPU
@zipcpu
Oct 4, 2018
Wow, lots of new twitter followers just joined. Welcome! Just to give you an opportunity to get to know me and the ZipCPU blog, here's a bit about me and what you can expect here: zipcpu.com/blog/2018/10/0… Again, welcome!
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Zip CPU
@zipcpu
Sep 18
This stack exchange post has a good description of the problems with using AES-CTR for memory encryption. I love the included pictures. They tell the story well. crypto.stackexchange.com/questions/59/t…
Zip CPU
@zipcpu
Sep 17
Whoever thought AES-CTR could be used to secure memory ... is offering an expensive encryption that looks good but offers zero security.
Zip CPU
@zipcpu
Sep 17
One of the differences between ASIC and FPGA design is the initial statement. ASICs don't support them. To build IP that works across technologies, I've had to be very careful where, when, and how I use such statements. In many cases, I've had to remove them over time when my
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@intothefloyd
Sep 16
Replying to @zipcpu
They don't, as long as you define their initial state in register declaration to avoid X's in simulation, and of course to get the initial state that you want, whether 0 or 1.
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Zip CPU
@zipcpu
Sep 17
Some time ago, I posted an article on how to move values and strobes across clock domains. The module was powerful, very versatile, and easy to work with. It had one flaw: it required a reset that would active in both clock domains at the same time, then synchronously release.
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