ZeroRISC

@ZeroRISC_

End-to-end open silicon security, from design through manufacturing to every field update. 🪸

Boston, MA

ZeroRISC
@ZeroRISC_
May 27
Pavona Launches Open-Hardware Ecosystem for Secure Chips (IEEE Spectrum) 🪸 spectrum.ieee.org/pavona-open-so…
ZeroRISC
@ZeroRISC_
May 26
Pavona: the open-source ecosystem for composable secure silicon. (launched today!) pavona.org 🪸🪸🪸🪸🪸🪸 Launch members: Analog Devices, Meta, Qualcomm, Winbond, ZeroRISC, Tenstorrent, Agile Analog, CrossBar, Baochip, SIMPLE-Crypto, Oxford, & MPI
ZeroRISC
@ZeroRISC_
May 11
Benchmarks are hard. Cryptographic benchmarks are harder. 📊⏱️ New post-quantum algorithms like ML-DSA can be incredibly difficult to benchmark, because their runtimes can vary depending on random values, meaning lots of time-consuming tests are needed to estimate performance.
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ZeroRISC
@ZeroRISC_
Feb 3
Fast. Flexible. Future-proof. Pick three. 📷📷 After sharing how we achieved ~3x performance on core RSA operations, we’re now giving a tour of how our cryptographic library can support a root of trust in everything from IoT to a BMC. [1/3]
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ZeroRISC
@ZeroRISC_
Jan 20
Lighting-fast crypto in pure assembly? 🏎️💨 Building on our post from last week, we’re sharing the technical details behind our 3.43x RSA speedup from implementing Chinese Remainder Theorem (CRT) modular exponentiation in our embedded cryptography library. [1/2]
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