DVCon India
September 1-3, 2026

Thanks For a Great Conference!

Special thanks to all our attendees, speakers, exhibitors, sponsors, and everyone who made DVCon India 2025 a success!

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Lifetime Achievement Award

Dr. V Veerappan, Tessolve

DVCon India Exemplary Contribution in Design/Verification - Company

Intel

Outstanding Contribution in Design/Verification - Individual

Ashok Kumar Natarajan, Google

Woman Achiever in Semiconductor Industry

Namratha Jaisimha

Best Educational Institution

Indian Institute of Technology, Palakkad

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Best Paper Award - General

Winner

Strategic Optimization of process parametric sampling
Pankaj Sharma
Intel

Runner-Up

Design and development of a hybrid out of order RISC-V processor module
Rajesh Jain, Mayuri G, Ashish M, Sourav R
NXP

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Best Paper Awards - Formal

Winner

Breaking barriers: Formal verification in complex compressor controller architecture
Namitha R, Usharani B, Rahul D, Sarsij S
Intel

Runner-Up

Uncovering Hardware vulnerabilities: Formal verification for security focussed negative testing
Vedprakash M, Ravi M
Intel

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Best Poster Awards

Winner

Novel and optimized solution to accelerate gate level simulations for complex SoC
Viral V, Sunil K, Ravikiran B, Garima S, Pradeepkumar S
Samsung

Runner-Up

Test Smarter, not harder: GNN powered automation for Post-Silicon Validation
Venkata Ajay K
Intel

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Social Media Spotlight Awards

Pre-DVCON Hype Award

Jeet Gandhi

Most Reached Post Award

Nihar Shetty

Highest Post Award

Atharv Naik

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Design Contest

Winners

I2CS_tvaritas
Shravan Narayan Sunil, Joel Dan Philip and Mukund Rathi
IIIT Kottayam

1st Runner up

Synth-Z
Thuvaragan Sooriyakumaran, Prabath Wijethilaka and Sundarbavan Thanaraj
University of Moratuwa

2nd Runner up

HYPERNUCS
Nikhil Patel, Rhythm Patel and Chippagiri Vamsi Krishna
Sardar Vallabhbhai National Institute of Technology

Software-defined hardware design relies on AI and intelligent verification

The design landscape has evolved dramatically. Exploding complexity, tighter timelines, and a shift to software-defined hardware design have turned functional verification into a gold mine of innovation. Every step in the verification flow is impacted including analog/mixed signal verification, RTL simulation, and hardware- assisted verification.

Using a software-defined approach to hardware design means the system's logic and functionality are defined and controlled primarily by software. At times this even allows for runtime reconfiguration and dynamic optimization of hardware components to meet changing requirements. This contrasts with traditional hardware-driven design, where the system is heavily based on fixed hardware. The advantage of software-driven design is that it offers greater flexibility, personalization, and the ability to reuse hardware for new problems.

In parallel, AI is transforming hardware design by assisting with tasks like design verification, component selection, and even automated layout and routing. AI- powered tools can accelerate design cycles, improve performance, and reduce errors.

This presentation explores the challenges of software-defined hardware design and its impact on functional verification tools and methodologies.

Presenter: Jean-Marie Brunet

Title: Vice President and General Manager of HW Assisted Verification, Siemens

The SDC 'Root-of-Trust' problem, and how we solve it

Timing constraints continue to be a major challenge to SoC design closure, even with more tools & methodologies being created to address piecemeal parts of the problem. This talk will focus on the unique challenge presented by timing constraints - how the design team establishes a single "source-of-truth" to drive signoff and retains the golden source and extends it as a root-of-trust across the design flow and into SoC integration.

Presenter: Dr. Sam Appleton

Title: CEO, Ausdia Inc

Re-engineering Engineering for AI Chip Design, Verification, and Optimization

Artificial Intelligence (AI) has transfixed the attention of the world and is infusing the electronics landscape from cloud-to-edge, including HPC, data center, PCs, smartphones, automotive, robots and many more devices. Architects and design teams are creatively producing AI engines that meet specific AI model and end-market application requirements. This new era of workload-specific AI accelerators necessitates new design, optimization, and verification strategies that must be performed in the context of the power and performance requirements of the end-market application. This new generation of customized chips driven by software workloads requires innovative, advanced and AI-assisted methodologies to ensure successful tapeouts in an increasingly complex, cost-driven, and fast time to value (TTV) environment. Hear how industry leaders are addressing these challenges from silicon to system and paving the way for further advancements in this new AI-driven era of pervasive intelligence.

Presenter: Vikas Gautam

Title: Vice President, Engineering, Synopsys

Power. Performance. Proofs: Scaling Formal for the AI-Driven Compute Revolution

AI is driving an explosive rise in custom compute, demanding architectures that balance performance, power efficiency, and security. While hyperscalers rely mostly on proprietary, GPU-centric designs, open-source RISC-V offers a flexible alternative-especially for Edge AI. Achieving optimal performance-per-watt means smarter design: tuning microarchitecture, NoCs, floating-point precision, and storage with HBMs and caches. In this talk, we present a breakthrough approach from Axiomise to scalable formal verification, combining abstraction-based methods with custom tool automation. Our solution addresses the full spectrum of challenges in verifying custom silicon, including PPA trade-offs and complex floating-point logic. Using mathematical proofs, we detect deep bugs, deadlocks, and livelocks-delivering formal at scale for the AI era.

Presenter: Dr. Ashish Darbari

Title: CEO and CTO, Axiomise

AI-Driven EDA: Evolving Trends and Technologies

Artificial Intelligence is the next leap in Electronic Design Automation, bringing unprecedented optimization and abstraction to verification. This keynote will share Cadence's vision for the journey of agentic AI-from Level 1 assistive tools to Level 5 fully autonomous agents-evolving from smart helpers to systems that plan, decide, and optimize verification with minimal human guidance. As AI advances through these levels, it will dramatically boost productivity, catch issues earlier, shorten schedules, and free engineers to focus on breakthrough innovation.

Presenter: Alok Jain

Title: Corporate VP - R&D, Cadence

AI-powered Chip Design: Spec to Silicon

In today's AI era, chip design is no longer the sole domain of traditional chipmakers. Industry giants - OEMs like Apple and Samsung, and software powerhouses like Microsoft, Amazon, and Meta - are all building their own chips to drive differentiation in products and services. AI is not just enhancing chip design; it's revolutionizing it. From boosting productivity to improving first-time silicon success, AI-powered EDA tools are becoming indispensable. We are witnessing a fundamental shift, where AI is not just an aid - but a necessity that redefines every stage of the semiconductor value chain. As the semiconductor industry enters this bold new chapter, it demands visionary engineers with deep domain expertise - leaders who can drive and shape this AI-led transformation. Join us on this transformative journey as we unlock the boundless possibilities of AI-powered Chip Design, enabling efficient chip design and revolutionizing the landscape of next-generation AI Chips.

Presenter: P R Sivakumar

Title: Founder and CEO, Maven Silicon

AI-Driven Design and Verification: Scaling Complexity with Intelligence

AI is becoming increasingly vital in semiconductor design and verification due to the growing complexity of chips and the need for faster development cycles. AI-driven solutions are under rapid exploration and implementation across the design cycle as they are designed to enhance the scale, speed, and complexity that traditional methods are increasingly struggling with. As chips become more intricate and timelines shrink, the ability to automate repetitive tasks, analyze massive datasets, and predict outcomes with high accuracy is enabling us to utilize AI as a transformative tool to augment design tasks, optimize performance, and predict issues early, enhance test generation, bug detection, and significantly reduce time-to-market.

The talk focuses on opportunities for the convergence of AI into the chip design cycle, specifically focused on the areas of Physical Design and Verification.

Presenter: Jayanth Thimmaiah

Title: Senior Director, Memory Technology, Sandisk