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@chipsalliance

CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

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🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

Popular repositories Loading

  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 4.6k 646

  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

    Scala 3.7k 1.2k

  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.8k 269

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

    Python 1.2k 371

  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 921 235

  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 747 179

Repositories

Showing 10 of 112 repositories
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel’s past year of commit activity
    Scala 4,551 Apache-2.0 646 351 (1 issue needs help) 146 Updated Jan 27, 2026
  • caliptra-rtl Public

    HW Design Collateral for Caliptra RoT IP

    chipsalliance/caliptra-rtl’s past year of commit activity
    SystemVerilog 128 Apache-2.0 73 101 (2 issues need help) 27 Updated Jan 27, 2026
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 135 Apache-2.0 83 221 (12 issues need help) 85 Updated Jan 27, 2026
  • t1 Public
    chipsalliance/t1’s past year of commit activity
    Scala 309 Apache-2.0 44 18 28 Updated Jan 27, 2026
  • verilator Public Forked from verilator/verilator

    Verilator open-source SystemVerilog simulator and lint system

    chipsalliance/verilator’s past year of commit activity
    SystemVerilog 41 753 0 0 Updated Jan 27, 2026
  • caliptra-mcu-sw Public

    Caliptra MCU Software

    chipsalliance/caliptra-mcu-sw’s past year of commit activity
    Rust 21 Apache-2.0 38 122 (8 issues need help) 32 Updated Jan 27, 2026
  • i3c-core Public
    chipsalliance/i3c-core’s past year of commit activity
    SystemVerilog 43 Apache-2.0 18 16 5 Updated Jan 27, 2026
  • sv-tests-results Public

    Output of the sv-tests runs.

    chipsalliance/sv-tests-results’s past year of commit activity
    HTML 7 6 0 0 Updated Jan 27, 2026
  • Caliptra Public

    Caliptra IP and firmware for integrated Root of Trust block

    chipsalliance/Caliptra’s past year of commit activity
    372 Apache-2.0 57 70 12 Updated Jan 27, 2026
  • sv-tests Public

    Test suite designed to check compliance with the SystemVerilog standard.

    chipsalliance/sv-tests’s past year of commit activity
    SystemVerilog 357 ISC 86 47 (4 issues need help) 28 Updated Jan 26, 2026
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