Technical Program
All times shown in Pacific Standard Time (UTC-8).
Sunday, February 22, 2026
Workshops and Tutorials are listed separately (All Day)
Sunday Reception
Monday, February 23, 2026
| 08:30 AM-08:45 AM |
Welcome | |
| 08:45 AM-09:30 AM |
An Introduction to Efinix, a new breed of FPGA company Jay Schleicher, Senior Vice President Software Engineering at Efinix |
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| 09:30 AM-10:30 AM | Paper Session I: CAD |
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Hardware Accelerated FPGA Divide-and-Conquer Page Placement in Milliseconds Ezra Thomas (University of Pennsylvania), Jing Li (University of Pennsylvania), André DeHon (University of Pennsylvania) |
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RND: A Mixed-Grained Parallel Routing Framework with Region-based Net Decomposition for UltraScale FPGAs Wenhao Lin (The Chinese University of Hong Kong), Zewen Li (The Chinese University of Hong Kong), Xinshi Zang (The Chinese University of Hong Kong), Evangeline F.Y. Young (The Chinese University of Hong Kong) |
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Finding and Understanding Bugs in FPGA Place-and-Route Engines Ollie Cosgrove (Imperial College London), Alastair F. Donaldson (Imperial College London), John Wickerson (Imperial College London) |
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| 10:30 AM-11:15 AM | Poster Session I & Break |
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| 11:15 AM-12:35 PM | Paper Session II: Machine Learning |
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KANELÉ: Kolmogorov-Arnold Networks for Efficient LUT-based Evaluation (Best Paper Candidate★) Duc Hoang (Massachusetts Institute of Technology), Aarush Gupta (Massachusetts Institute of Technology), Philip C Harris (Massachusetts Institute of Technology) |
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CXL-SpecKV: A Disaggregated FPGA Speculative KV-Cache for Datacenter LLM Serving (Best Paper Candidate★) Dong Liu (Yale University), Yanxuan Yu (Columbia University) |
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Enabling Efficient SpMM for Sparse Attention on GEMM-Optimized Hardware with Block Aggregation Tianchu Ji (Stony Brook University), Niranjan Balasubramanian (Stony Brook University), Michael Ferdman (Stony Brook University), Peter Milder (Stony Brook University) |
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HGQ: High Granularity Quantization for Real-time Neural Networks on FPGAs Chang Sun (California Institute of Technology), Zhiqiang Que (Imperial Collage London), Thea Aarrestad (ETH Zurich), Vladimir Loncar (Institute of Physics Belgrade), Jennifer Ngadiuba (FermiLab), Wayne Luk (Imperial College London), Maria Spiropulu (California Institute of Technology) |
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| 12:35 PM-02:00 PM | Lunch | |
| 02:00 PM-03:20 PM | Paper Session III: High-Level Synthesis |
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Out with LSQs: Custom Circuits for Memory Access Reordering in Dynamic HLS (Best Paper Candidate★) Rouzbeh Pirayadi (EPFL), Ayatallah Elakhras (EPFL), Mirjana Stojilović (EPFL), Paolo Ienne (EPFL) |
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EagerlyElastic: Correct-by-Construction Eager Execution in Dynamically-Scheduled HLS Shun Katsumi (ETH Zurich), Emmet Murphy (ETH Zurich), Lana Josipović (ETH Zurich) |
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HACE: HLS-Tool-Agnostic CDFG Extraction from RTL Designs Carmine Rizzi (ETH Zurich), Sebastian Pfeiler (ETH Zurich), Lana Josipović (ETH Zurich) |
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HiLFS: FPGA-Orchestrated File System for High-Level Synthesis YoungSeok Na (University of Pennsylvania), Linus Y. Wong (University of Pennsylvania), André DeHon (University of Pennsylvania), Jing "Jane" Li (University of Pennsylvania) |
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| 03:20 PM-04:00 PM | Poster Session II & Break |
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| 04:00 PM-05:00 PM | Paper Session IV: Industry Track |
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Hyperscale FPGA Engineering Systems at Microsoft Rob Rydberg (Microsoft Corporation), Madison N. Emas (Microsoft Corporation), John Demme (Microsoft Corporation), Ana Ibarra (Microsoft Corporation), Kara Kagi (Microsoft Corporation), Brandon Klouchek (Microsoft Corporation), Abhijeet Lawande (Microsoft Corporation), Todd Massengill (Microsoft Corporation), David J. Powers (Microsoft Corporation), Andrew Putnam (Microsoft Corporation) |
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Bridging the Gap: A Module-Context Modeling Methodology for Hyperscale FPGA Applications Madison N. Emas (Microsoft Corporation), Austin Baylis (Microsoft Corporation), Greg Stitt (University of Florida) |
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AI-Assisted Copilot Automation for Reliable FPGA Verification at Hyperscale Linh Nguyen (Microsoft Corporation), Nguyen Le (Microsoft Corporation), Tony-Dat Tran (Microsoft Corporation), Jagannath Panduranga Rao (Microsoft Corporation), Andrew Putnam (Microsoft Corporation) |
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| 05:00 PM-06:30 PM | Adjourn & Steering Committee Meeting | |
| 06:30 PM-08:30 PM | Industrial Expo (& Reception) |
Tuesday, February 24, 2026
| 09:00 AM-09:15 AM | Announcements | |
| 09:15 AM-10:00 AM |
Democratizing FPGA-Accelerated Infrastructure for the AI Era: The MangoBoost Perspective Eriko Nurvitadhi, Co-Founder and the Chief Product Officer of MangoBoost, Inc |
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| 10:00 AM-11:00 AM | Poster Session III & Break |
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| 11:00 AM-12:00 PM | Paper Session V: Architecture |
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vFPGA: Towards Sub-us Reconfiguration via 3D FPGA and Packaging Co-Design Nikhil K. Cherukuri (University of Minnesota), Sharad Nag (University of Minnesota), Pragnya S. Nalla (University of Minnesota), Ashish K. Kola (University of Minnesota), Chetan S. Gadireddi (Arizona State University), Kevin Dai (University of Minnesota), Jae-sun Seo (Cornell Tech), Zhenman Fang (University of Minnesota), Jeff Zhang (Arizona State University), Yu Cao (University of Minnesota) |
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TDM Signal Grouping and Package Pin Assignment for 2.5D Multi-FPGA Systems with Lookahead Placement Jiarui Wang (Peking University), Runzhe Tao (Peking University), Jing Mai (Peking University), Xun Jiang (Peking University), Shenghua Wang (S2C Inc.), Cuiliu Yang (S2C Inc.), Haoyu Jie (S2C Inc.), Kan Huang (S2C Inc.), Richard Y. Sun (S2C Inc.), Yibo Lin (Peking University) |
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UDP: A Universal DSP Packing Framework for Low-bitwidth MAC Acceleration on FPGAs Jundong Wu (University of Science and Technology of China), Zhendong Zheng (University of Science and Technology of China), Lei Gong (University of Science and Technology of China), Chao Wang (University of Science and Technology of China), Xuehai Zhou (University of Science and Technology of China) |
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| 12:00 PM-01:30 PM | Lunch | |
| 01:30 PM-02:40 PM | Paper Session VI: Computing Engines |
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SORCERI: Streaming Overlay Acceleration for Highly Contracted Electron Repulsion Integral Computations in Quantum Chemistry Philip Stachura (Simon Fraser University), Xin Wu (Paderborn Center for Parallel Computing, Paderborn University), Christian Plessl (Paderborn Center for Parallel Computing, Paderborn University), Zhenman Fang (Simon Fraser University / University of Minnesota) |
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Hummingbird+: Advancing FPGA-based LLM Deployment from Research Prototype to Edge Product Jindong Li (Institute of Automation, Chinese Academy of Sciences), Tenglong Li (Institute of Automation, Chinese Academy of Sciences), Guobin Shen (Institute of Automation, Chinese Academy of Sciences), Dongcheng Zhao (Institute of Automation, Chinese Academy of Sciences), Qian Zhang (Institute of Automation, Chinese Academy of Sciences), Yi Zeng (Institute of Automation, Chinese Academy of Sciences) |
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TeLLMe: An Efficient End-to-End Ternary LLM Prefill and Decode Accelerator with Table-Lookup Matmul on Edge FPGAs Ye Qiao (University of California, Irvine), Zhiheng Chen (University of California, Irvine), Yifan Zhang (University of California, Irvine), Yian Wang (University of California, Irvine), Sitao Huang (University of California, Irvine) |
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Gatling-V: An FPGA-based RISC-V Vector Core with Single-Issue, Multiple In-Flight Instruction Execution (short) Farid Chalabi (University of British Columbia), Guy Lemieux (University of British Columbia) |
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| 02:40 PM-03:40 PM | Paper Session VII: Applications |
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HERA: A Bandwidth-efficient Accelerator for Fully Homomorphic Encryption on HBM-enabled FPGA Zhihan Xu (University of Southern California), Rajgopal Kannan (DEVCOM Army Research Office), Viktor Prasanna (University of Southern California) |
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EdgeSort: A Sub-100 ns, Line-Rate FPGA Streaming Sorter Greg Stitt (University of Florida), Wesley Piard (University of Florida), Christopher Crary (University of Florida) |
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MegaTurbo: A Scalable FPGA-based Engine for MegaFlow Classifier in Open vSwitch Sheng Lan (Peking University Shenzhen Graduate School), Ying Li (Southern University of Science and Technology), Zhongxian Liang (Harbin Institute of Technology), Wenjun Li (Pengcheng Laboratory), Yao Xin (Guangzhou University), Ying Wan (Southeast University), Hui Li (Peking University Shenzhen Graduate School), Weizhe Zhang (Harbin Institute of Technology) |
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| 03:40 PM-04:00 PM | BPA & Closing remarks |
Poster Session 1 (Monday, February 23, 2026)
10:30am – 11:15am
| Title | Authors |
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| Attest Like Software: Formally-Verified Software-Programmable Proof of Execution Architecture Using SoC FPGAs | Fatemeh Arkannezhad (UCLA), Nader Sehatbakhsh (UCLA) |
| Hardware Software Optimizations for Fast Model Recovery on Reconfigurable Architectures | Bin Xu (Arizona State University), Ayan Banerjee (Arizona State University), Sandeep K. S. Gupta (Arizona State University) |
| A2H-MAS: An Algorithm-to-HLS Multi-Agent System for Automated and Reliable FPGA Implementation | Jie Lei (University of Technology Sydney), Ruofan Jia (Xidian University), J. Andrew Zhang (University of Technology Sydney), Hao Zhang (University of Technology Sydney) |
| Chext: A Domain-specific Language for Safe and Agile Elastic Dataflow Accelerators | Canberk Sönmez (EPFL), Mohamed Shahawy (EPFL), Paolo Ienne (EPFL) |
| Exploring Real-Time Power Electronics Simulation on AMD AIEs | Shouyu Du (Clemson University), Zhenyu Xu (Clemson University), Miaoxiang Yu (Clemson University), Jillian Cai (Clemson University), Yeonho Jeong (University of Rhode Island), Tao Wei (Clemson University) |
| A Model-Hardware Co-design Framework for Robust and Efficient CNN-Based SAR ATR | Sachini Wickramasinghe (University of Southern California), Tian Ye (University of Southern California), Cauligi Raghavendra (University of Southern California), Viktor Prasanna (University of Southern California) |
| OpenPCIe: An Open-Source PCIe Controller | Idris Somoye (Morgan State University), David Jovel (Morgan State University), Lamia Mannan (Morgan State University) |
| CAD-in-the-Cloud: Protecting FPGA Design Privacy via Redacted Netlists | Eddie Rydell (Brigham Young University), Reilly McKendrick (Brigham Young University), Jeff Goeders (Brigham Young University) |
| Striking the Balance: GEMM Performance Optimization Across Generations of RyzenTM AI NPUs | Endri Taka (The University of Texas at Austin), Andre Roesti (Advanced Micro Devices, Inc.), Joseph Melber (Advanced Micro Devices, Inc.), Pranathi Vasireddy (Advanced Micro Devices, Inc.), Kristof Denolf (Advanced Micro Devices, Inc.), Diana Marculescu (The University of Texas at Austin) |
| Chrono-Fabric: A Decoupled Hierarchical Framework for Cycle-Accurate Coordination in Multi-FPGA Systems | Congwu Zhang (Institute of Computing Technology, Chinese Academy of Sciences), Panyu Wang (Institute of Computing Technology, Chinese Academy of Sciences), Yazhou Wang (Institute of Computing Technology, Chinese Academy of Sciences), Bibo Yang (Institute of Computing Technology, Chinese Academy of Sciences), Mingyu Chen (Institute of Computing Technology, Chinese Academy of Sciences), Yungang Bao (Institute of Computing Technology, Chinese Academy of Sciences), Ke Zhang (Institute of Computing Technology, Chinese Academy of Sciences) |
| [From Poster Session 3] PROM: Protection against Reverse Engineering Attacks through Programmable Logic Macros | Pravin Gaikwad (University of Florida), Aritra Dasgupta (University of Florida), Sudipta Paria (University of Florida), Peyman Dehghanzadeh (University of Florida), Jonathan Cruz (University of Florida), Swarup Bhunia (University of Florida) |
Poster Session 2 (Monday, February 23, 2026)
3:20pm – 4:00pm
| Title | Authors |
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| A High-level Synthesis Toolchain for the Julia Language | Benedict Short (Imperial College London), Ian McInerney (Imperial College London), John Wickerson (Imperial College London) |
| Towards Scheduling of Pipelined Dataflow Graphs in MLIR | Gabriel Rodriguez-Canal (EPCC, University of Edinburgh), Nicolas Bohm Agostini (Pacific Northwest National Laboratory), Ankur Limaye (Pacific Northwest National Laboratory), Vito Giovanni Castellana (Pacific Northwest National Laboratory), Joseph Manzano (Pacific Northwest National Laboratory), Antonino Tumeo (Pacific Northwest National Laboratory), Maurice Jamieson (EPCC, Universtiy of Edinburgh), Nick Brown (EPCC, University of Edinburgh) |
| Multi-Port Memory with Bidirectional Ports for FPGAs Using XOR and LVT Methods | Kevin Townsend (Unaffiliated) |
| NysX: An Accurate and Energy-Efficient FPGA Accelerator for Hyperdimensional Graph Classification at the Edge | Jebacyril Arockiaraj (University of Southern California), Dhruv Parikh (University of Southern California), Viktor Prasanna (University of Southern California) |
| A Cloud-Native FPGA-Accelerated Framework and Methodology for Hardware Verification | Irfan Waheed (SilverLining EDA), Wajahat Riaz (SilverLining EDA), Babar Sohail (SilverLining EDA) |
| HFRWKV: A High-Performance Fully On-Chip Hardware Accelerator for RWKV | Shijie Liu (Sun Yat-sen University), Zhenghao Zeng (Sun Yat-sen University), Han Jiao (Sun Yat-sen University), Yihua Huang (Sun Yat-sen University) |
| Synchronized CPU-FPGA Tracing for Heterogeneous Platforms | Nicolas Deloumeau (Polytechnique Montréal), Tarek Ould-Bachir (Polytechnique Montréal), David Evans (Ciena Corporation), Andrew Handke (Ciena Corporation), Jamie Sanderson (Ciena Corporation), Francois Tetreault (Ciena Corporation) |
| MARU: An ML-Based Framework for Area Estimation from FPGA Resource Usage | Tarun Kholay (The University of Texas at Austin), Anup Ashok Kedilaya (The University of Texas at Austin), Aman Arora (Arizona State University), Jaydeep P. Kulkarni (The University of Texas at Austin), Lizy K. John (The University of Texas at Austin) |
| Closing the Loop on FPGA Verification: An Iterative Framework for Maximizing Routing Resource Coverage | Ruthwik Reddy Sunketa (Arizona State University), Aman Arora (Arizona State University) |
| Analysis and Optimization of Input-Dependent Stream Processing Pipelines on FPGAs | Shashank Obla (Carnegie Mellon University), Bin Li (Intel Corporation), James C. Hoe (Carnegie Mellon University) |
Poster Session 3 (Tuesday, February 24)
10:00am – 11:00am
| Title | Authors |
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| FARE: A Fine-grained Pipelined Reconfigurable FlashAttention Kernel | Kaushikkumar S. Rathva (Indian Institute of Science (IISc)), Aakarsh Alam (Indian Institute of Technology (IIT), Kharagpur), Srini Srinivasan (Advanced Micro Devices, Inc. (AMD)), Sumit K. Mandal (Indian Institute of Science (IISc)) |
| [Presented in Poster Session 1] PROM: Protection against Reverse Engineering Attacks through Programmable Logic Macros | Pravin Gaikwad (University of Florida), Aritra Dasgupta (University of Florida), Sudipta Paria (University of Florida), Peyman Dehghanzadeh (University of Florida), Jonathan Cruz (University of Florida), Swarup Bhunia (University of Florida) |
| Improving Area Efficiency in Synthesizable eFPGA with Multi-output Logic Cell and Domain-Specific Routing Architecture | Ryo Iwasaki (Kumamoto University), Tatsuya Sasaki (Kumamoto University), Yumi Iseki (Kumamoto University), Sota Kohata (Kumamoto University), Miyu Yoshida (Kumamoto University), Kenshu Seto (Kumamoto University), Masahiro Iida (Kumamoto University) |
| RISCBench: Benchmarking RISC-V Orchestration Efficiency in FPGA and FPGA-Like Computing Engines | Dave Ojika (Flapmax), Projjal Gupta (University of Florida), Preethi Budi (Flapmax), Herman Lam (University of Florida), Shreya Mehrotra (Altera Corporation) |
| AgRefactor: Refactoring for HLS Compatibility with a Self-Evolving Agentic Workflow | Yang Zou (Carnegie Mellon University), Zijian Ding (University of California, Los Angeles), Chi Wang (Google DeepMind), Yizhou Sun (University of California, Los Angeles), Jason Cong (University of California, Los Angeles) |
| ViM-Q: Energy Efficient Algorithm-Hardware Co-Design for Dynamically Quantized Vision Mamba Models | Shengzhe Lyu (City University of Hong Kong), Yuhan She (City University of Hong Kong), Patrick S. Y. Hung (City University of Hong Kong), Ray C. C. Cheung (City University of Hong Kong), Weitao Xu (City University of Hong Kong) |
| Modulation Recognition in a System-on-Chip (SoC) | John Wohlbier (Carnegie Mellon University, Software Engineering Institute), Daniel Bonness (The Pennsylvania State University, Applied Research Laboratory), Jodi Miller (The Pennsylvania State University, Applied Research Laboratory), Marika Schubert (Carnegie Mellon University, Software Engineering Institute) |
| CODESCA: Co-Design for Spectral Clustering Acceleration | Zhengyan Liu (Tianjin University), Ce Guo (Imperial College London), Zehuan Zhang (Imperial College London), Qiang Liu (Tianjin University), Wayne Luk (Imperial College) |
| FlexMSM: A Flexible FPGA-Based Accelerator for Multi-Scalar Multiplication with Reconfigurable Modular Arithmetic and Optimized Pippenger Scheduling | Cheng Chen (Shandong University), Gangqiang Yang (Shandong University), Hongchao Zhou (Shandong University), Hailiang Xiong (Shandong University), Zhiguo Wan (Zhejiang Lab) |
| A Hierarchical Methodology for Hardware Design Comparison in HPC Workloads | Doru Thom Popovici (Lawrence Berkeley National Laboratory), Mario Vega (Lawrence Berkeley National Laboratory), Angelos Ioannou (Lawrence Berkeley National Laboratory), Fabien Chaix (Foundation for Research and Technology - Hellas (FORTH)), Dania Mosuli (University of Houston Clear Lake), Blair Reasoner (University of Houston Clear Lake), Tan Nguyen (Lawrence Berkeley National Laboratory), Xiaokun Yang (University of Houston Clear Lake), John Shalf (Lawrence Berkeley National Laboratory) |
| Gatling-V: An FPGA-based RISC-V Vector Core with Single-Issue, Multiple In-Flight Instruction Execution (short) | Farid Chalabi (University of British Columbia), Guy Lemieux (University of British Columbia) |
Workshops and Tutorials are listed separately
