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Andreas Olofsson
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Andreas Olofsson

@zeroasic
Moved to aolofsson.bsky.social
Cambridge, MA
zeroasic.com
Joined January 2011
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  • Pinned
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    Andreas Olofsson
    @zeroasic
    Dec 13, 2022
    I am done with Twitter. See you in the real world.
  • user avatar
    Andreas Olofsson
    @zeroasic
    Sep 18, 2024
    Finally, a proper "pip/npm for hardware", major SiliconCompiler upgrade, SiliconCompiler.com . Try it! import siliconcompiler import umi # design chip = siliconcompiler.Chip("top.v) chip.use(umi) # pulls in dependencies # your code chip.run()
  • user avatar
    Andreas Olofsson
    @zeroasic
    Jul 31, 2024
    Get ready for the post Moore wafer-scale era. Check out our latest paper showing RTL simulation of a million cores processor. (RISC-V) arxiv.org/abs/2407.20537
  • user avatar
    Andreas Olofsson
    @zeroasic
    Apr 3, 2024
    We just open sourced Logik, our light weight Python based FPGA toolchain. No more TCL and 100GB binary blob downloads! Please try it,we are proud of this work.🙏 github.com/zeroasiccorp/l… $ python -m pip install --upgrade logik
  • user avatar
    Andreas Olofsson
    @zeroasic
    Mar 21, 2024
    This post shows how to build and verify your own chip(let) in Python. Writing SV testbenches is not fun, Switchboard and SiliconCompiler improves life quality! 😉Try it out and let us know what you think.
    Image
    Bring Your Own RTL to Zero ASIC's Chiplet Ecosystem
    From zeroasic.com

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