Zip CPU

@zipcpu

FPGA design engineer and blogger, placing particular emphasis on test and formal verification

Gisselquist Technology, LLC,

Pinned
Zip CPU
@zipcpu
Oct 4, 2018
Wow, lots of new twitter followers just joined. Welcome! Just to give you an opportunity to get to know me and the ZipCPU blog, here's a bit about me and what you can expect here: zipcpu.com/blog/2018/10/0… Again, welcome!
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Zip CPU
@zipcpu
22h
The issue is the missing reset. 2FF synchronizers need asynchronous reset. The reset must have a source, common to both clock domains, and it needs to have a synchronized release in each domain.
Zip CPU
@zipcpu
Sep 16
What do you think, anyone see a bug here? It's a basic 2FF CDC crossing, from one clock to another ...
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Zip CPU
@zipcpu
Sep 16
What do you think, anyone see a bug here? It's a basic 2FF CDC crossing, from one clock to another ...
6
Zip CPU
@zipcpu
Sep 14
Fun story ... A customer was complaining about IO's coming out of a chip they had produced, using a design I had worked with. The IO's worked well, and had the right output voltage (1.8v IIRC), unless they were driven with a 250MHz pattern--at which point the waveforms only
4
Zip CPU
@zipcpu
Sep 6
May God be praised.