Welcome FPGA engineers to join the official WeChat technical group.

Clickthe blue textto follow us at FPGA Home – the largest pure FPGA engineering community in China.

Introduction: When we conduct FPGA schematic and PCB design, we involve the pin definitions and package-related information of FPGA chips. This article provides relevant references for the Xilinx 7 Series FPGA, aiming to assist FPGA hardware developers. Through this article, you can learn about:

• How the pins of the Xilinx 7 Series FPGA are defined.

• How to download the FPGA pin file (Pinout file) during schematic design.

1. Xilinx 7 Series FPGA Pin Definition

Table 1-1 lists the pin definitions in the 7 Series FPGA package. Note: Table 1-12 separately lists dedicated general user I/O, as well as multifunction I/O marked with IO_LXXY_ZZZ# or I/O_XX_ZZZ_#, where ZZZ represents one or more additional functions. If multifunction I/O is not used for special purposes, they can be used as ordinary I/O, which is something we need to pay attention to during hardware design.

Table 1-1, Xilinx 7 Series FPGA Pin Definition

The FPGA device pins are divided by bank, with each bank independently powered to allow FPGA I/O to adapt to different voltage standards, enhancing the flexibility of I/O design. Each user bank includes 50 I/O pins or 24 pairs of differential pairs (48 differential signals), with one single-ended pin at the top and one at the bottom. Figure 1 provides an example of the user bank IO schematic for the K325T chip.

Figure 1, K325T Chip User Bank IO Schematic

In the figure, we can see the two single-ended signals circled in red. The _CC clock pin circled in green can be used as user I/O when not used for clock input. Additionally, we can see the VREF pin marked in blue. When this BANK I/O is used for DDR memory interfaces, it needs to provide the threshold voltage required for pseudo-differential signals, at which point the _VREF_ pin needs to connect to the reference voltage required by the DDR peripherals. For further analysis of other I/O pins, please refer to the pin definition explanation in Table 1-1.

2. Downloading Xilinx 7 Series FPGA Pinout Files

How can we obtain the pin definitions for each FPGA when conducting schematic library design? In the UG475 official document, Chapter 2, the section on 7 Series FPGAs Package Files provides links to the Pinout definitions for all devices in the 7 Series, categorized by FPGA device family and device package. The official website provides both CSV and TXT formats for the Pinout files, which we can choose flexibly.

Figure 2, FPGA Pinout Download Links

Figure 3, Downloading Pinout from Xilinx Official Website

When we open a .TXT format Pinout, as shown in Figure 4, we can see that the file is divided into 8 columns, containing all the key information required for the design schematic: pin number, pin name, pin DDR memory grouping, pin BANK number, auxiliary group (VCCAUX), super logic region (SLR), I/O pin type (configuration, HR, HP, transceiver pins, etc.), and NC pin information related to device Pin-to-Pin compatibility.

Figure 4, Example of Pinout File Content

Welcome FPGA, embedded, signal processing engineers to follow our public account.

The largest FPGA WeChat technical group in the country

Welcome everyone to join the national FPGA WeChat technical group. This group has tens of thousands of engineers, a community of engineers who love technology, where FPGA engineers help and share with each other, creating a strong technical atmosphere!Hurry up and invite your friends to join!!

Press and hold to join the national FPGA technical group.

FPGA Home Component City

Advantage component services, if you need, please scan to contact the group owner: Jin Juan Email: [email protected] Welcome to recommend to procurement.

ACTEL, AD part advantage ordering (operating the full series):

XILINX, ALTERA advantage stock or ordering (operating the full series):

(The above devices are part of the models, for more models please consult group owner Jin Juan)

Service philosophy: FPGA Home component self-operated city aims to facilitate engineers to quickly and conveniently purchase components. After years of dedicated service, our customer service is spread across large listed companies, military research units, and small and medium enterprises. The greatest advantage is to emphasize the service-first concept, and achieve fast delivery and favorable prices!

Directly operated brands: Xilinx, ALTERA, ADI, TI, NXP, ST, E2V, and more than a hundred component brands, especially good at dealing with components subject to embargoes from the US and Europe.We welcome engineer friends to recommend us to procurement or consult us personally!We will continue to provide the best service in the industry!

Official thanks to the brands of the FPGA technical group: Xilinx, Intel (Altera), Microsemi (Actel), Lattice, Vantis, Quicklogic, Lucent, etc.