Xilinx FPGA Learning Notes

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1. Timing Design

Method 1: Implementing through state machines, controlling the FPGA with Verilog to make it fast when necessary and slow otherwise.

Method 2: Running a CPU in the FPGA

Using C code to handle complex logic control sequences while real-time processing is done in Verilog, which can be controlled by the C code. The CPUs currently supported by Xilinx FPGAs include Microblaze, ARM9, and POWERPC, where Microblaze is a soft core, and the other two are hard cores.

(1) A soft core is a CPU core implemented in code, offering flexible configuration;

(2) A hard core is a circuit that has been pre-made and cannot change.

Soft cores offer good flexibility but consume FPGA resources. Hard cores do not consume FPGA resources and provide better speed and performance. For example, Xilinx’s DDR memory controller is a type of hard core with very high operating speed.

2. Basic Syntax

1. always @(), where the parentheses contain *, indicating it is always sensitive;

2. (1) <= Non-blocking assignment, where all statements in an always block update together.

(2) = Blocking assignment, or assigning a value to a signal, where this statement is executed immediately in the always block.

Non-blocking assignment

always @(posedge clk)begin
      a <= b;
       c <= a;
end

The execution result is that the value of a is b, and the result of c remains a.

Blocking assignment

always @(posedge clk)begin
     a = b;
      c = a;
end

The execution result is that the value of a is b, and the result of c is also b.

Generally, we use non-blocking assignment statements as they help control synchronization effectively.

3. Preprocessing Commands
`include file1.v
`define X=1;
`define Y;
`ifdef Y
     Z = 1;
`else
      Z = 0;
`endid

Sometimes we need some common macro parameters, which we can place in a file, such as XXX.v. We can then `include XXX.v to include the macro parameters defined in that file.

3. Small Exercise

1. Design of an Adder

module adder(
input [3:0] a,
input [3:0] b,
input cin,
output [3:0] sum,
output cout
);

assign {cout,sum} = a + b + cin;
endmodule

RTL View

RTL Technical Schematic

Simulation Code

`timescale 1ns / 1ps  //1ns simulation scale, 1ps simulation precision
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
// Create Date: 2017/10/22 10:47:58
// Design Name:
// Module Name: simu
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
// Dependencies:
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//////////////////////////////////////////////////////////////////////////////////

module simu(

);

reg [3:0] a;
reg [3:0] b;
reg cin;

wire cout;
wire [3:0] sum;

reg [4:0] i,j; // Intermediate variables

adder inst(
.a(a),
.b(b),
.cin(cin),
.cout(cout),
.sum(sum)
);

initial begin
a =0; b=0; cin=0;
for(i=1;i<16;i=i+1)
#10 a = i;
end

initial begin
for(j=1;j<16;j=j+1)
#10 b = j;
end

initial begin
$monitor($time,,,"%d + %d + %b = {%b,%d}",a,b,cin,cout,sum);
#160 $finish; // Simulation ends after 160ns
end

endmodule

Simulation Waveform

Print Output Result

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