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CXL IP User Guide redirect to intel.com and access denied.
Hey, guys, I am interested in CXL IP inside Agilex7 device. Before I purchase the DK-DEV-AGI027-RA-B board, I want to read the User Guide and the Example Design User Guide to try the CXL demo. But the documents link listed on the webpage below: Compute Express Link (CXL) IP | Altera https://www.intel.com/content/www/us/en/secure/content-details/862292/agilex-7-r-tile-compute-express-link-cxl-1-1-2-0-fpga-ip-user-guide.html?wapkw=cxl%20ip%20user%20guide https://www.intel.com/content/www/us/en/secure/content-details/862293/agilex-7-r-tile-compute-express-link-cxl-fpga-ip-design-example-user-guide.html?wapkw=cxl%20ip%20user%20guide redirect me to intel.com and after I registered and login in, I can only see access denied. So how can I get access to these 2 documents. Thanks. Joseph9Views0likes1CommentR-Tile Avalon Streaming PIPE Direct x16: Locks COM(K28.5) Symbols correctly but some lanes do not.
Hello, I am implementing a custom soft PCIe/CXL link layer and LTSSM using R-Tile Avalon Streaming IP in PIPE Direct mode, configured as x16. At the moment, link training does not reliably move forward because some lanes receive valid COM/K-code alignment, but the following ordered-set symbols are corrupted. Environment Device / board: AGIB027R29A IP: R-Tile Avalon Streaming FPGA IP for PCI Express Mode: PIPE Direct Link width: x16 Current focus: Gen1 training / Polling / Configuration Custom implementation: custom LTSSM custom symbol lock using COM (K28.5) custom TS1/TS2 decode logic Symptom In Polling.Active and Polling.Configuration , I can see that some lanes captures/decodes TS1/TS2 correctly, but some lanes do not. For example, in the attached SignalTap screenshot: Lane 9 appears to decode the TS2 sequence correctly. Lane 8 shows COM (K28.5) and PAD (K23.7) correctly, but the symbols after that are unstable / corrupted. From the screenshot: Lane 9 example: K28.5, K23.7, K23.7, D24.0, D30.0 D00.0, repeated Lane 8 example: K28.5, K23.7 are visible, but the following TS2 fields fluctuate and do not remain valid/stable. So it looks like: COM-based symbol lock is working at least partially but after COM/PAD, the ordered-set contents on some lanes(random) are corrupted before my soft IP can decode them correctly To verify whether this was caused by my own logic, I captured the affected lanes directly in SignalTap using the first raw 10-bit RX data from the PIPE Direct IP (`ln*_pipe_direct_pipe_rxdata_o`), before any symbol lock/decoding stage in my soft IP. I searched for the COM symbol directly in this raw 10-bit stream and confirmed that the corruption is already present at the PIPE Direct IP output. So this does not appear to be caused by my combinational decode logic; the raw RX data delivered by the IP is already corrupted on those lanes. What I already checked I already checked the following items carefully: Gen1 rxdata interpretation I only decode valid 10-bit portions for Gen1 I do not interpret the don't-care bits in rxdata[31:10] and rxdata[63:42] rxdatavalid qualification TS decode / symbol shift only happens when rxdatavalid0/1 are valid Sampling clock SignalTap capture is done in the corresponding lane RX clock domain not with a shared TX/fabric clock Reset sequence pld_pcs_rst_n_i release is gated after per-lane tx_transfer_en_o I also reviewed cdrlock2data, reset_status_n, phystatus, powerdown sequencing Deskew-related status active channels are detected Current question At this point, I suspect one of the following: lane-specific analog/RX quality issue inside or before PIPE Direct output lane-specific reset/power-up timing issue internal alignment / deskew behavior that I am misunderstanding some required PIPE Direct control/sideband setting that I am missing What I would like to ask In PIPE Direct x16 Gen1, if one lane shows valid K28.5 / K23.7 but the following TS2 symbols are corrupted, what should I check first on the R-Tile side? Are there any lane-specific PMA / RX / PIPE Direct controls that should be reviewed for this symptom? Is there any recommended way to determine whether this is: a true lane analog/RX problem, a deskew/alignment issue, or a reset/bring-up sequence issue? Are there any known recommendations for validating lane integrity directly at the PIPE Direct output during Polling.Configuration?Why does the Single Floating Point Variable Streaming Reverse FFT IP produce an incorrect output when the input order is set to Natural?
Description Due to a problem in the Quartus® Prime Software version 25.3.1 and earlier, the "Natural" option for setting "Input Order" is incorrectly available for selection and unsupported when generating the FFT IP. This option is available when using the following parameters: Direction: "Reverse", Data Flow: "Variable Streaming", Representation: "Single Floating Point". Resolution This problem is scheduled to be fixed in release 26.1 of the Quartus® Prime Software with the removal of the unsupported “Natural” option. Additional Information This problem affects the FFT IP in Quartus® Prime Software versions 17.0 to 25.3.1.Why does Ashling* RiscFree* IDE for Altera FPGAs software version 25.4.1 turns compiler warnings into errors?
Description In the Ashling* RiscFree* IDE for Altera FPGAs software version 25.4.1 (31 st Oct 2025) and later, you might see compilation error related to the following errors: Implicit int types (-Werror=implicit-int) Implicit function declarations (-Werror=implicit-function-declaration) Typos in function prototypes (-Werror=declaration-missing-parameter-type) Incorrect uses of the return statement (-Werror=return-mismatch) Using pointers as integers and vice versa (-Werror=int-conversion) Type checking on pointer types (-Werror=incompatible-pointer-types) This is due to an update in GCC 14 – GNU: Certain warnings are now errors, which affects future GCC versions. For more information, Ashling* RiscFree* IDE for Altera FPGAs software version 25.3.1 (1 st August 2025) is using GCC 13.2. Ashling* RiscFree* IDE for Altera FPGAs software version 25.4.1 (31 st Oct 2025) is using GCC 15.2. Thus, Ashling* RiscFree* IDE for Altera FPGAs software version 25.4.1 (31 st Oct 2025) and future versions are affected. Note that Ashling* RiscFree* IDE for Altera FPGAs software version 25.4.1 (31 st Oct 2025) is paired with Quartus ® Prime Pro Edition software version 26.1. Resolution GNU recommends resolving all the new errors for better code quality. If necessary, you may refer to the workaround – GNU: Turning errors back into warnings. In Board Support Package Editor, add "-fpermissive" in hal.make.cflags_user_flags.Why does simulation elaboration fail with port width mismatch for the F-tile Ethernet Hard IP 400GE-8 DR example design generated with VHDL when using QuestaSim* or Riviera-PRO* simulator?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1, when running simulation for the F-Tile Ethernet Hard IP 400GE-8 Dynamic Reconfiguration (DR) Example Design generated with VHDL and using Questa* Sim or Riviera-PRO* simulator, you may observe the following port width mismatch error during elaboration: # Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/eth_f_hw/IP_INST[0]/hw_ip_top/dut File: ./eth_f_hw_ip_top_400g.sv Line: 707 # ** Fatal: (vsim-3363) The array length (4) of VHDL port 'anlt_link' does not match the width (8) of its Verilog connection (1st connection). # Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/eth_f_hw/IP_INST[0]/hw_ip_top/dut File: ./eth_f_hw_ip_top_400g.sv Line: 707 # FATAL ERROR while loading design # Error loading design Error loading design This occurs due to a mismatch between the array length of the VHDL port and the width of its Verilog connection in the generated design. Resolution To work around this problem, you may use one of the following methods: Update the MAX_ETHPORT parameter in the eth_f_hw_ip_top module to 4: parameter MAX_ETHPORT = 4; (Change the value to 4 as shown above.) Use the following suppress switch in the vsim do file: elab -suppress 3363 This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.4Views0likes0CommentsDiscover What’s New in Quartus® Prime Pro 26.1
3 MIN READ Quartus Prime Pro 26.1 improves FPGA development with faster performance, a new drag-and-drop design tool (Visual Designer Studio), better power/thermal analysis, and expanded IP support and debugging—making design workflows simpler and more efficient.58Views0likes0CommentsMCDMA IP D2H Queue Reset Failure during Channel Re-allocation
After successfully loading the binary and launching D2H (Device-to-Host) operations on my FPGA, the first channel is allocated successfully and transfers data without issue. However, when I try to allocate another channel, it fails with a "queue reset failed" error. Initially, during the initialization phase, all 512 channels were checked and appeared available. Environment: Device Family: [Agilex 7] Quartus Version: [24.1] Driver/Software: VFIO based IP Config: MCDMA configured with 512 channels Why is this happening? How to rectify the same ?35Views0likes5CommentsArrow AXE5 Eagle Board JTAG issue
Hi, I have an AXE5 eagle board. The Quartus Programmer on Auto-Detect does show the usb blaster3 but the device is named UNKNOWN_364F0DD instead of A5ED065BB32AES4. What do you think could be the issue? BTW I am on Linux RHEL 8. I am using Arrow blaster and used FTProg to flash it as USB Blaster 3 as suggested by guide22Views0likes0CommentsKnow-How: Set Up a Floating License (Step-by‑Step Walkthrough)
#sharing #debug #altera #alldevices #license Disclaimer: This article is provided as-is for educational purposes only, without warranty of any kind. Use the information at your own risk. Always verify implementations in your specific environment and consult official Altera documentation for production deployments. Introduction This guide explains how to set up a floating license for Altera® FPGA tools. The instructions and screenshots are based mainly on the Windows* operating system, but the same concepts apply to Linux systems. Overview: What You Need Before Starting Before you begin, make sure you have the following: A valid floating license file (.dat) - For the examples below, this file will be referred to as float.dat. Access to the license server machine The license server’s hostname and NIC ID / Host ID Steps Step 1: Generate the Floating License File (SSLC) i. Log in to the Self Service Licensing Center (SSLC). ii. Select your product entitlement, for example: - Quartus Prime - Questa iii. Choose one of the following: - An existing computer with FLOAT license type - Or select + New Computer, in the Create Computer, choose FLOAT license type, and enter the license server NIC ID / Host ID 4. Generate and download the license file (.dat). Step 2: Edit License File i. Open the downloaded license file and update it based on the instructions provided in the User Guide Section 6.4.4.1: Setting Up a License File in the License Server: Altera Documentation and Resources Center Helpful Tips 1: ----------------------------------------------------- START ----------------------------------------------------- To find the license server hostname - Open a Command Prompt and run: hostname - Install only the latest license daemons. Remove all older versions, and keep only the most recent ones. Required daemons: FlexNet License Daemon for FPGA software (64‑bit) Includes: alterad (Altera daemon), lmgrd, lmtools, lmutil (These are used later in Step 3.) FlexNet License Daemon for Siemens ModelSim / Questa FPGA software (64‑bit) Includes: saltd (Siemens Advanced Licensing Toolkit Daemon) Download link: Flexlm License Daemons for FPGA Software | Altera *If you’re running a floating license server for Siemens licenses, you need to manually change the VENDOR daemon line in the license file from mgcld to saltd. It is optionally to put user-defined port numbers for the alterad and saltd daemons unless you have specific port numbers that allow firewall access. In this case, I left it empty. ------------------------------------------------------ END ------------------------------------------------------ ii. At the end of Step 2, your license should looks similar like below (Windows): Important to note: Use “” if there is space in the path. Step 3. Launching the Licensing Server The requisites to configure a new license server are: System administration (Administrator) privileges. A valid license.dat floating license file. (Linux only) To run the FLEXlm lmgrd license server manager, make sure that the /usr/tmp directory exists. There are two methods to launch the license server: a) Using the Command Line Interface (CLI) i) Open a Command Prompt (Windows) or Terminal (Linux). ii) Change to the directory where the lmgrd executable is located. iii) Start the license server by running command: lmgrd -c <license.dat> Example: lmgrd -c float.dat This command starts the license server using the specified license file. You will see a few windows pop up showing that the daemons are running. Helpful Tips 2: ----------------------------------------------------- START -----------------------------------------------------To make things easier - skipping the a) ii) step, you can add the path directory that contains lmgrd to your system’s Path environment variable. Once it’s added, you can run the lmgrd command directly from any directory in the Command Prompt. ------------------------------------------------------ END ------------------------------------------------------ iv) To verify the license status. Run: lmutil lmstat –c <license.dat> Example: lmutil lmstat –c float.dat How to Read the above info: Line Note License server status: 1234@<hostname> This contains the license server name needed for the license environment variable setup. It is displayed in the form of <port number>@<hostname> License file(s) on <hostname>: <License Path> : This showed which license file is being used. This is where you make sure the license file you are using is correct. <Hostname>: license server UP (MASTER) v11.19.6 This mean the license server is up successfully. Vendor daemon status (on <hostname>): This showed the vendor daemon status and the daemon version you are using. Make sure the version used is the latest version available. v) Stop the license server: lmutil lmdown -c <license.dat> Example: lmutil lmdown –c float.dat Helpful Tips 3: ----------------------------------------------------- START ----------------------------------------------------- The above command just display the overall status of the license. You can add -a option in the command to report out the verbose list of available licenses and its total numbers of seat, example: lmutil lmstat –a –c <license.dat> Example: lmutil lmstat –a –c float.dat To check a specific feature: lmutil lmstat –c <license.dat> -f <feature name> Example to check the Questa Altera FPGA Edition license: lmutil lmstat –c float.dat -f intelqsim View command options: lmutil lmstat -help ------------------------------------------------------ END ------------------------------------------------------ b) Using the Graphic User Interface (GUI) 1. Right‑click lmtools and select Run as Administrator. 2. In the Service / License File tab, select Configuration Using Services. 3. Switch to the Config Services tab and configure the required fields below: 4. Click Save Service. 5. Go to the Start / Stop / Reread tab and click Start Server to launch the service. 6. Click Stop Server to shut it down. Helpful Tips 4: ----------------------------------------------------- START ----------------------------------------------------- The GUI performs the same actions as the command line, but is easier to visualize. For debugging, the CLI provides more detailed output. If something fails, always check: - Server Status - Debug Log Diagnose license or feature issues using CLI: - lmutil lmdiag -c <license.dat> <feature_name> If using GUI, you can run diagnostics from the Server Diags tab. ------------------------------------------------------ END ------------------------------------------------------ Conclusion This guide provides a complete walkthrough for setting up a floating license server for Altera FPGA tools. Following these steps should help ensure a reliable and functional license environment.PCIe Hard IP - Can 'valid' De-assert Between SOP and EOP During DMA Read Completion?
Product / IP: Intel PCIe Hard IP (Avalon-ST Interface Device Family: Cyclon 10 GX Reference Manual: https://docs.altera.com/r/docs/683647/18.0/arria-10-and-cyclone-10-gx-avalon-streaming-interface-for-pci-express-user-guide/datasheet I am an FPGA Design Engineer currently working on verifying the application layer logic interfacing with Intel's PCIe Hard IP over the Avalon Streaming (Avalon-ST) interface. As part of the verification effort, I have developed an Avalon-ST Bus Functional Model (BFM) that mimics the RX-side behavior of the PCIe Hard IP — specifically, how it presents TLP data (DMA Read Completions) to the downstream application logic. During simulation, my BFM generates scenarios where the 'valid' signal is de-asserted between 'startofpacket (SOP)' and 'endofpacket (EOP)' — i.e., mid-packet gaps or "bubbles" are introduced within a single TLP transfer. When this occurs, the application layer logic does not handle it correctly, causing functional failures. Before proceeding with fixing the application logic to handle this case, I need to confirm from Intel whether this behavior is actually possible on the real PCIe Hard IP hardware Question 1: On the RX Avalon-ST interface, when the PCIe Hard IP is acting as the SOURCE (driving TLP completion data toward user application logic), is it possible for the 'valid' signal to be de-asserted between SOP and EOP within the same TLP packet? Question 2: If yes, under what conditions can this occur? Question 3: Does the Intel PCIe Hard IP Reference Manual explicitly document this behavior anywhere? If so, could you point to the relevant section?40Views0likes6Comments
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Quartus Prime Pro 26.1 improves FPGA development with faster performance, a new drag-and-drop design tool (Visual Designer Studio), better power/thermal analysis, and expanded IP support and debugging—making design workflows simpler and more efficient.
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Altera is extending the availability of its Agilex®, MAX® 10, and Cyclone® V FPGA families through 2045 to support long-lifecycle applications like industrial, aerospace, and medical systems. This helps customers avoid costly redesigns and ensures reliable, long-term supply, reinforcing Altera as a trusted partner for decades-long deployments.
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