OpenHW Foundation (formally the OpenHW Group) is a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software. OpenHW provides an infrastructure for hosting high quality open-source HW developments in line with industry best practices. Please see our website for membership information, latest news, and further resources.
| Working Group | Repo | Description |
|---|---|---|
| Cores TG | Core-v-cores roadmap | |
| CTG meetings and minutes | ||
| In Active Development | CVA6 | 6-stage, application-class and embedded-class configurable core family |
| CVW | 5-stage, application-class core with education focus | |
| CV32E40PV2 | 4-stage, embedded-class core extending CV32E40Pv1 with FPU and PULP extensions | |
| CV32E40S | 4-stage, embedded-class core with security focus | |
| CV32E20 | 2-stage, embedded-class microcontroller core and core complex | |
| CV32E40PX (repo TBD) | 4-stage, embedded-class core extending CV32E40Pv2 with RVB/RVK/RVP and CV-X-IF | |
| Completed | CV32E40P | 4-stage, embedded-class core implementing PULP extensions at TRL5 |
| CVA5 | 5-stage, FPGA-optimized application-class core at TRL3 | |
| CV32E41P | 4-stage, embedded-class core prototyping Zfinx and Zce at TRL3 | |
| Inactive project | CV32E40X | 4-stage, embedded-class core supporting X-Interface |
| Verification TG | VTG meetings and minutes | |
| CORE-V Verif | Common test bench for OpenHW Cores | |
| FORCE RISC-V | Advanced RISC-V instruction set generator | |
| Software TG | SWTG meetings and minutes | |
| CORE-V GNU Tools | GNU Tools Project for embedded-class CORE-V cores | |
| CORE-V LLVM | LLVM Tools Project for embedded-class CORE-V cores | |
| CORE-V FreeRTOS Kernel | FreeRTOS Kernel for embedded-class CORE-V cores | |
| CORE-V FreeRTOS | FreeRTOS for embedded-class CORE-V cores | |
| CORE-V QEMU | QEMU emulator for CORE-V-MCU | |
| CORE-V SDK | SDK and IDE for 4-stage CORE-V cores | |
| CVA6 SDK | Software tools for the CVA6 core | |
| Interconnect TG | ||
| CV-HPDCACHE | High performance L1 Data Cache | |
| CV-MESH (repo TBD) | Coherency framework based on Open Piton | |
| CV-TCCC | Tightly-coupled cache coherence for CVA6 | |
| CORE-V VISION APU (repo TBD) | Machine learning SoC including CVA6 and CV-VEC | |
| CVA6-Platform | Multi-core CVA6 with CV-MESH intended for software testing | |
| CORE-V-POLARA-APU | Multicore CVA6/CVVEC ASIC with CV-MESH | |
| CORE-V-POLARA-DEVKIT (repo TBD) | Development board for Polara APU | |
| Hardware TG | HWTG meetings and minutes | |
| CORE-V-MCU | ASIC and FPGA MCU implementation of CV32E40P | |
| CORE-V-MCU-DEVKIT | Devkit for CORE-V-MCU | |
| Technical Working Group | OpenHW project dashboard | |
| Project Description Folders | ||
| OpenHW Project process and templates |
