697 questions
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Can I insert a folder (directory) instead of a file as a BlackBox in Chipyard?
I am trying to configure an MMIO Peripheral (= MMIO Accelerator, 11page) consisting of a 4x4 NoC in Chipyard. In this process, I would like to insert a SystemVerilog-based NoC as a BlackBox. However, ...
- reputation score 1
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68
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How do I peek a Bundle in ChiselSim?
I'm trying to test a circuit with ChiselSim. The input to the circuit is a Bundle (without nesting) which I can poke without any problem, but when I try to peek the output of the same type I get an ...
- reputation score 148
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131
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To what extent can I expect the original FIRRTL compiler to optimize?
For now I am still using the final release of the original FIRRTL compiler that was archived in 2024.
I am using to software compilers going to great lengths to optimize code, performing constant ...
- reputation score 1925
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mill debugger intellij in Xiangshan project
I'm trying to debug the XiangShan RISC-V SoC project using IntelliJ IDEA with Mill and BSP.
I've followed all recommended steps (scala, the mill build tool, and the IntelliJ debugger) but breakpoints ...
- reputation score 5
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54
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How do I initialize a Vec inside a Bundle literal in Chisel?
I'm trying to test a module which takes as input a UInt that follows the structure of this Bundle:
class Sample(n_attr: Int, n_classes: Int, n_depths: Int, info_bit: Int, tree_bit: Int) extends Bundle{...
- reputation score 148
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45
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Adding an AttributeAnnotation to a SyncReadMem object in latest Chisel versions
I am trying to annotate a SyncReadMem object with with a verilog attribute in the newer versions of Chisel (>3.6.1). I'm using Chisel mostly for FPGA development, and so for the different FPGA ...
- reputation score 11
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274
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In Chisel3, how to add `mark_debug = "true"` attribute to an internal signal in the output SystemVerilog file?
As stated in the title, I want to easily make any internal signals in my design to be available for debugging in Vivado (mostly ILA). In version 3.5.3 I was able to use a snippet to do it, however in ...
- reputation score 58
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115
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How to disable `ifdef FIRRTL_BEFORE_INITIAL` in Chisel?
When generating code, I get garbage like
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
initial begin
automatic ...
- reputation score 1
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111
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In RISCV, is Each thread has a own PC value in multithreading Program?
Im currently working on a Hard ware for Data Race detect
So I track each instructions and made history table for race detect.
I made C program for Intended data race and Track instructions by PC value
...
- reputation score 11
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728
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How to generate Verilog rather than SystemVerilog from Chisel?
Here is my GCD.scala
package gcd
import chisel3._
class GCD extends Module {
val io = IO(new Bundle {
val value1 = Input(UInt(16.W))
val value2 = Input(UInt(16.W))
val ...
- reputation score 23
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146
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How to obtain emulator binary in latest rocket-chip using mill and chisel 5.0.0?
I've setup Chisel 5.0.0 and firtool as I explained in this other question. I also installed successfully mill and rocket-tools as instructed here and here.
This prepared the stage for getting the ...
- reputation score 319
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44
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error message chisel when call a module in another module
I have defined the class fu_data_t and cap_result_t in a scala file, which is used in the class crevokeModule in another scala file. Then, crevokeModule is used in the class AluDataModule. Finally, ...
- reputation score 1
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109
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Chisel Template Not Functioning Windows 11 - Cannot run program "which": CreateProcess error=2, The system cannot find the file specified
After having cloned the template project for Chisel (https://github.com/chipsalliance/chisel-template) I tried running sbt test, and I got the following error in the file /src/test/scala/gcd/GCDSpec:
&...
- reputation score 47
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103
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Using each delayed flop states in chisel ShiftRegister
I am writing chisel for the following FIR circut (specifically to understand ShiftRegister in chisel as this can be done easily using NextReg in chisel).
I have written this code:
class My4ElementFir(...
- reputation score 29
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384
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How can i generate vcd file with recent version of Chisel?
I used to generate the vcd file through chiseltest like below.
import chisel3._
import chiseltest._
import org.scalatest.flatspec.AnyFlatSpec
class MyModuleSpec extends AnyFlatSpec with ...
- reputation score 69
