#AMD released the #Zen5 Optimization Guide 58455 1.0 with official instruction latency and throughput list:
amd.com/content/dam/am…
According to this pdf, the latency of simple instructions is just 1 clk.
I've summarized the #AMD#Zen6 info into a #Zen5 analog chart. It seems that the homogeneous era is over at #AMD as well, there will be SKUs that will have 256b and 512b FPUs same time. I think the ISA homogeneity will remain.
These are my expectations for #AMD#Zen6. #Zen5 is a very strong architecture, but it has some weak point that Zen6 will hopefully fix. (The Zen5 512/256b FPU size is not segmented along the Classic/Dense axis, but along the MCM=Multi-Chip Module/SCM=Single-Chip Module axis)
