Frame out

Inspiration

Our inspiration for this project was to learn and develop our hardware and fpga skills.

What it does

Display short videos at 96x54 resolution with a maximum of 14 frames and 7.5 frames per second.

How we built it

We worked towards the middle. One group worked on the Verilog side while another worked on the Python side. The Verilog side was created with an inferred rom storing each frame and a Verilog file reading each frame one by one on every clock cycle. The Python side worked on a system to convert moving images (ie videos) into a format that can be easily interpreted by Verilog.

Challenges we ran into

We ran into challenges for both the Verilog side and the Python side. For Verilog, moving from Cb to Cr to give the monitor colour, getting the coordinates for pixels and the size of the screen(with headers incorporated), putting the code for the images into memory (e.g ram.), and debugging the issue of the monitor not displaying frames.

Accomplishments that we're proud of

Being able to display a gif of 4 frames at a high frame rate, and with consistent colour for each pixel in the frame.

What we learned

Verilog coding

• Inferring Rom to make code more reusable
• Python RGB decoding from images
• Using Python to build memory for the ROM in Verilog
• Manipulating arrays and timing in Verilog to generate a pixelated image

What's next for Frame out

On the Python side, restricting the colour gamut to 8-bit colour can drastically decrease file sizes and therefore compile time. It would slightly reduce the quality of the image for the upside of supporting more frames or a higher resolution. On the Verilog side, upgrading hardware and improving memory, speed, and efficiency.

Built With

• python
• verilog