Introduction:

With the rapid development of artificial intelligence technology, AI chips have become the core driving force propelling the progress of intelligent systems. They are the cornerstone for implementing complex algorithms and data processing tasks, and are crucial for building intelligent applications. In the evolution of AI chips, GPUs have long dominated the market with their powerful graphics processing capabilities and advantages in parallel computing. However, the continuous innovation of technology and diversification of application scenarios are challenging the dominant position of GPUs, indicating that the future of AI chips may no longer be entirely dependent on GPUs.

This article will delve into the future trends of AI chips, analyzing the challenges and limitations currently faced by GPUs, and looking forward to how emerging technologies such as FPGA and ASIC are gradually rising to become the new favorites in the AI field. We will assess how these technologies meet the needs of specific AI applications and how they affect the competitive landscape of the AI chip market. Discussing their strategic choices and development potential in the trend of AI chip diversification is also an essential path for the distributed chip resource network UtilityNet.

Part-1: The Current Landscape of AI Chips

AI chips are the core hardware that enables artificial intelligence applications, specifically designed to handle machine learning algorithms and deep neural networks. The main types of AI chips on the market include GPUs, FPGAs, and ASICs, with TPU being a type of ASIC that is optimized for specific computational tasks.

In the layout of artificial intelligence computing architectures, the model of CPUs working in conjunction with acceleration chips has become a typical AI deployment scheme. The CPU acts as the provider of basic computing power, while the acceleration chip is responsible for enhancing computational performance, playing a crucial role in improving computational efficiency and reducing energy consumption. Common AI acceleration chips can be divided into three major categories based on their technical paths: GPUs, FPGAs, and ASICs. Each type of chip has its unique design philosophy and technical advantages.

GPU (Graphics Processing Unit) is an electronic circuit designed for parallel processing, initially created for fields such as graphics and video rendering. However, its parallel processing capability makes it the preferred choice for current AI and deep learning tasks.

FPGA (Field Programmable Gate Array) is a semi-custom chip that offers a flexible solution. Users can reprogram and configure the hardware according to their own needs. The advantages of FPGAs include addressing the shortcomings of custom circuits and overcoming the limitations of the number of gates in traditional programmable devices. They allow flexible compilation at the hardware level, with lower power consumption than CPUs and GPUs. The disadvantages include the difficulty of hardware programming languages, a higher development threshold, and higher chip costs and prices. FPGAs are faster than GPUs and CPUs because they have a customized structure.

ASIC (Application Specific Integrated Circuit) is an integrated circuit designed and manufactured according to the specific needs of a product, with a higher degree of customization compared to GPUs and FPGAs. It is a chip tailor-made for specific tasks. The computational power of ASICs is generally higher than that of GPUs and FPGAs, but the design and manufacturing costs are higher. The strong professionalism reduces their versatility; once the algorithm changes, the computational power will drop significantly, requiring a redesign.

It is particularly worth mentioning the TPU within ASICs, such as Google’s TPU and SOPHGO’s high-performance TPU, which are processors optimized for specific types of machine learning tasks. The design of TPUs is optimized for specific mathematical operations of deep learning algorithms, providing high-performance computing capabilities while maintaining low energy consumption.

The choice of AI chips depends on various factors, including application scenarios, performance requirements, cost considerations, and development time. As AI technology continues to advance and market demand grows, the landscape of AI chips is also constantly evolving. In the following chapters, we will delve into the advantages, limitations, and roles of these chip types in the future development of AI.

Part-2: The Rise and Advantages of GPU

During the early development phase of artificial intelligence, the GPU (Graphics Processing Unit) quickly rose to prominence due to its exceptional parallel processing capabilities, becoming the main force in AI computing. Initially designed to handle complex graphics and visual effects, the highly parallel architecture of GPUs was unexpectedly well-suited for performing the extensive mathematical operations required by deep learning algorithms. Moreover, mature ecosystems, such as NVIDIA’s CUDA platform, have provided developers with a wealth of tools and libraries, further solidifying the position of GPUs.

Natural Advantages of Parallel Computing:

The core advantage of GPUs lies in their ability to process thousands of threads simultaneously, making them more efficient than traditional CPUs (Central Processing Units) when executing parallel computing tasks. Matrix multiplications and other mathematical operations in deep learning algorithms can be broken down into numerous small tasks that can be processed in parallel, where GPUs play a significant role.

Mature Ecosystem:

Companies like NVIDIA have established a robust GPU computing ecosystem by providing platforms such as CUDA (Compute Unified Device Architecture). These platforms offer developers a rich set of software libraries, frameworks, and tools, making GPUs more competitive in scenarios that require rapid iteration and adaptation to new algorithms. The maturity of this ecosystem greatly reduces the barrier to entry and accelerates the popularization and innovation of AI technology.

Versatility and Flexibility:

GPUs were originally used for graphics rendering, but over time, their application fields have gradually expanded. Today, GPUs not only play a central role in graphics processing but are also widely used in deep learning, big data analysis, and other fields. This versatility allows GPUs to meet a variety of application needs, while specialized chips like ASICs and FPGAs are limited to specific scenarios. Some compare GPUs to a versatile multi-functional kitchen utensil, suitable for various cooking needs. Therefore, in most AI applications, GPUs are considered the best choice. Correspondingly, being multifunctional and broad often comes with a lack of “refinement” in specific domains.

Although GPUs have inherent advantages in AI computing, they also face challenges in terms of cost, power consumption, and limitations in specific application scenarios. In the following chapters, we will explore these challenges and analyze how other types of AI chips may provide potential solutions.

Part-3: Limitations and Challenges of GPU

Although GPUs currently dominate the AI field, they are not without limitations, and some inherent issues are gradually emerging. Cost, power consumption, and performance bottlenecks in specific application scenarios are the main challenges faced by GPUs. As AI technology rapidly develops, GPUs require greater flexibility and adaptability to meet the evolving demands.

Cost Issue:

The high cost of GPUs is one of the main challenges they face. The price of high-performance GPUs is expensive, which limits the investment capacity of small and medium-sized enterprises and startups in AI projects. Moreover, as AI models become increasingly complex, the number and performance of GPUs required are also continuously increasing, further driving up costs.

Power Consumption and Heat Issues:

While GPUs provide high-performance computing, they also come with high power consumption and heat generation. This not only limits the application of GPUs in mobile and edge devices but also poses challenges in terms of heat dissipation and energy efficiency for data centers. With the growing global focus on sustainable development and energy efficiency, these issues have become more prominent.

Competition from Specialized Hardware:

As AI technology matures, an increasing number of specialized hardwares such as ASICs and FPGAs are entering the market. These hardwares are optimized for specific AI tasks, offering higher performance and energy efficiency ratios. For example, Google’s TPU and SOPHGO’s high-performance TPU have outperformed traditional GPUs in certain deep learning tasks.

Co-design of Software and Hardware:

The versatility of GPUs is an advantage, but it also means they may not be the best choice for all AI tasks. As AI algorithms continue to evolve, the co-design of software and hardware is becoming increasingly important. Specialized hardware such as ASICs and FPGAs can be customized according to specific algorithms, thereby achieving better performance.

Supply Chain and Availability Issues:

The global chip shortage has affected various semiconductor products, including GPUs. The uncertainty of the supply chain brings risks to enterprises that rely on GPUs, forcing them to seek alternative solutions or increase inventory to cope with potential shortages.

Evolution of Algorithms and Models:

The rapid development of the AI field means that algorithms and models are also constantly evolving. GPUs need to continuously adapt to new computational demands, which may lead to their performance in some emerging fields being not as good as specialized hardware. For example, with the continuous increase in the size of neural network models, the demand for memory bandwidth and processing power is also increasing, which poses a challenge to GPUs.

Conclusion: The rise of GPUs in the AI field is indisputable, but their limitations and challenges are also evident. As technology develops and the market changes, GPUs need to continuously innovate and improve to maintain their leadership in the field of AI computing. At the same time, other types of AI chips, such as FPGAs and ASICs, may provide more attractive solutions in specific fields. In the next part, we will explore the flexibility and applications of FPGAs, and how they complement or challenge the position of GPUs in the AI field.

Part-4: The Flexibility and Applications of FPGA

FPGAs offer a solution that lies between general-purpose CPUs and specialized ASICs. Their programmability allows developers to customize hardware according to specific needs, thereby achieving greater flexibility and efficiency in AI computing.

Programmability:

The biggest advantage of FPGAs is their programmability. Users can reconfigure the hardware logic of FPGAs according to their own needs. This flexibility makes FPGAs adaptable to the ever-changing AI algorithms and application scenarios. Developers can design and optimize hardware for specific AI tasks, thereby achieving higher performance and efficiency than general-purpose hardware.

Rapid Iteration and Development:

In the process of AI research and development, rapid iteration is crucial. FPGAs allow researchers and engineers to quickly test and modify their designs, greatly accelerating the process of prototype development and experimentation. This capability is particularly valuable when exploring new AI algorithms or adjusting existing algorithms to adapt to new datasets.

Low Latency and Pipeline Processing:

FPGAs have the advantage of low latency when processing data, which is crucial for real-time AI applications. For example, in autonomous driving and robotics, fast response time is a key factor in ensuring safety. The pipeline processing capability of FPGAs makes them excellent for tasks such as video stream processing and network packet analysis.

Energy Efficiency:

Compared to GPUs, FPGAs usually have an advantage in terms of energy efficiency. This is because FPGAs can be precisely configured for specific tasks, avoiding unnecessary computation and power consumption. When processing AI tasks such as image recognition and speech recognition, FPGAs can achieve efficient computing with low energy consumption.

Customized Solutions:

FPGAs allow developers to create customized solutions for specific application scenarios. This customization is not only reflected in the hardware implementation of algorithms but also includes optimization of data flow and processing procedures. This makes FPGAs irreplaceable in certain fields, such as military, aerospace, and industrial automation.

Cost-effectiveness:

Although the initial development cost of FPGAs may be high, once the design is complete, their production cost is relatively low, especially in small-batch production. In addition, the reusability of FPGAs reduces the cost of hardware replacement in the long term.

Challenges and Development:

Despite the many advantages offered by FPGAs, they also face some challenges. For example, the development threshold of FPGAs is relatively high, requiring professional knowledge of hardware description languages. Moreover, the market penetration and ecosystem construction of FPGAs are not as mature as those of GPUs and ASICs.

In Part Four, we delve into the flexibility and applications of FPGAs, demonstrating their potential and advantages in the field of AI. As AI technology continues to develop, the programmability and customization capabilities of FPGAs will play a key role in specific application scenarios. In the next part, we will discuss the customization and efficiency of ASICs and how they contribute to the future of AI chips.

Part-5: Customization and Efficiency of ASIC

ASICs (Application-Specific Integrated Circuits) represent another significant direction in the development of AI chips. By being custom-designed for specific applications or tasks, they offer higher performance and energy efficiency ratios. Despite the high development costs, the cost-effectiveness and optimized performance of ASICs at scale make them strong competitors to GPUs.

Customized Design:

The core advantage of ASICs lies in their customized design. Unlike general-purpose chips, ASICs are designed from the ground up for specific algorithms or applications. This customization allows ASICs to achieve optimized performance for specific tasks in terms of processing speed, energy consumption, and chip area.

Performance Optimization:

Since the design of ASICs is specifically targeted at particular computational tasks, they typically provide higher performance for these tasks compared to general-purpose chips. For instance, in cryptocurrency applications such as Bitcoin mining, ASICs offer higher efficiency and lower energy consumption than GPUs.

Energy Efficiency:

The advantage of ASICs in energy efficiency is particularly pronounced. They eliminate unnecessary computations and functions found in general-purpose chips, thereby reducing energy consumption. In data centers that require large-scale deployment of AI models, the high energy efficiency ratio of ASICs can lead to significant savings in operational costs.

Cost-effectiveness:

Although the initial R&D and manufacturing costs of ASICs can be high, the per-unit cost can be significantly reduced once mass production is achieved. Moreover, due to the high efficiency of ASICs, the long-term operating costs are relatively low, making ASICs cost-effective for large-scale deployment.

Application Scenarios:

ASICs excel in specific application scenarios, such as voice recognition, image processing, and natural language processing. As AI technology continues to evolve, the application scenarios for ASICs are also expanding into other fields.

Challenges:

The main challenge of ASICs is their lower flexibility. Since ASICs are designed for specific tasks, if AI algorithms change, ASICs may need to be redesigned and manufactured again, which can lead to high time and cost expenditures.

Technological Advancements:

With the advancement of semiconductor technology, the design and manufacturing processes of ASICs are also continuously improving. For example, using more advanced manufacturing processes can enhance the performance and energy efficiency of ASICs while reducing costs.

Future Trends:

With the rapid development of AI technology, the position of ASICs in the AI chip market is becoming increasingly important. Especially in application scenarios that require high performance and efficiency, ASICs will be a key solution.

Conclusion: The customized design and high efficiency of ASICs give them a unique position in the field of AI chips. They provide an optimized combination of performance and energy efficiency for specific tasks, which has been proven in multiple domains. For instance, SOPHGO’s high-performance TPU is a manifestation of the ASIC concept, which is specifically optimized for machine learning and deep learning workloads, offering significant performance improvements and energy efficiency ratios. The design of SOPHGO TPU demonstrates how ASICs can meet the needs of specific AI applications through customized solutions, which is particularly prominent in high-performance computing and large-scale AI model training.

Although ASICs face challenges in flexibility and cost, their long-term cost-effectiveness and advantages in specific tasks remain significant. As AI technology continues to develop and the industry’s demand for efficient computing solutions increases, it is expected that the market share and influence of ASICs will continue to grow.

Part-6: Future Trends of AI Chips

The future of AI chips will be shaped by new materials, new architectures, and new algorithms. As the demands of AI applications continue to evolve, the future trends of AI chips point towards more efficient, more specialized, and smarter computing solutions, such as improving computational efficiency through integrated photonics or leveraging quantum effects.

The Rise of Heterogeneous Computing: The future of AI chips may no longer rely on a single type of processor. Heterogeneous computing, which combines various types of processors (such as CPUs, GPUs, FPGAs, ASICs) to handle different tasks, will become mainstream. This design can optimize performance and energy efficiency while reducing the complexity of the overall system.

Customization of Domain-Specific Chips: As AI applications become more diverse, the demand for domain-specific chips (DSAs) will grow. ASICs and FPGAs will continue to evolve to meet the needs of specific industries, such as healthcare, finance, and autonomous driving.

Neuromorphic Computing: Neuromorphic chips mimic the working principles of the human brain, improving computational efficiency by simulating the structure of neural networks. These chips are expected to achieve breakthroughs in processing sensor data and performing complex pattern recognition tasks.

Integration of Quantum Computing: The potential of quantum computing is gradually being recognized, and it may offer significant advantages in handling certain types of AI algorithms. Although quantum computing is still in its early stages, its integration with AI chips will be a long-term trend worth watching.

Expansion of Edge Computing: With the proliferation of Internet of Things (IoT) devices, AI processing will increasingly take place near the data source, reducing reliance on cloud computing. This will drive the development of edge AI chips, which need to provide efficient computing power within limited energy and space.

Energy Efficiency Optimization: The energy efficiency ratio will become a key consideration in AI chip design. With the global focus on environmental impact increasing, low-power AI chips will be more popular, especially in mobile devices and large-scale deployed AI applications.

New Materials and Manufacturing Technologies: New materials (such as silicon-based photonics, carbon nanotubes) and advanced manufacturing technologies (such as extreme ultraviolet lithography EUV) will be used to develop AI chips with stronger performance and smaller sizes.

Open-Source Hardware and Software Ecosystems: The establishment of open-source hardware and software ecosystems will promote the innovation and popularization of AI chip technology. By sharing designs and tools, developers can iterate and deploy AI solutions more quickly.

Security and Privacy Protection: As AI applications become more in-depth, chip-level security and privacy protection will become an important part of the design. Hardware-supported security features will be integrated into AI chips to prevent data leaks and unauthorized access.

Market Segmentation of AI Chips: The AI chip market will further segment to meet the application scenarios with different performance, cost, and energy efficiency needs. This will lead to more AI chip solutions optimized for specific tasks or industries in the market.

The future of AI chips will be an era of diversity and specialization. With the continuous advancement of technology, we expect to see more innovative solutions, such as Google’s TPU and SOPHGO high-performance TPU, which will drive the development of AI technology and provide customized optimization in specific fields. These trends will shape the next decade of AI chips, bringing smarter, more efficient, and safer computing experiences.

Summary

UtilityNet adoption of SOPHGO TPU is part of a strategy to achieve future technology compatibility and diversification, laying the foundation for the future integration of more types of AI chips and computing resources. The heterogeneous compatibility of various chips (hardware) and underlying software, as well as the optimization of computing resource scheduling, is a long-term strategic issue. The future of AI chips may no longer be a world dominated by GPUs alone. Diversified and customized chip technologies will provide a broader space for the development of AI. Continuous innovation and adaptability will be the key to the development of AI chip technology. The future landscape of chip development will be an era of diversity, customization, open innovation, and continuous progress. Various chip technologies will jointly promote the development of AI technology and software, as well as the underlying compatible system architecture, providing strong computing support for the arrival of an intelligent world. In this process, a company’s ability to innovate, adapt, and strategic vision will determine whether it can hold a place in the fierce market competition.

By now, most of us are aware of ChatGPT, Midjourney, and other amazing generative AI products. We use them for all sorts of tasks. The online media is filled with research and claims about how we are entering a new era of AI — one that is having an unprecedented impact on work and human creativity.

But the underlying technology for these remarkable products and solutions is highly dependent on infrastructure components. Chips (GPUs, TPUs…)

The scarcity of AI chips is exacerbated by Nvidia’s dominance in the market as a major supplier of these key components. On the other hand, instead of building and maintaining data centers equipped with computer servers and dedicated network equipment, tech companies typically choose to purchase AI chip access and computing power through cloud computing services offered by major companies such as Google, Microsoft, and Amazon.

As a result, tech companies’ need for chips this year is more pressing than money, engineering talent, hype or even profits.

The boom in AI technology has resulted in organizations having to wait a long time (sometimes nearly a year) to get the necessary AI chips from cloud providers. This situation has become an unexpected obstacle.

While large tech companies tend to have easier access to GPUs / TPUs with their strong resources, market reach and extensive networks, startups and academic researchers are at a disadvantage. Lacking the financial capabilities and strategic relationships that large corporations have, these small businesses struggle to acquire the computing power they need to advance their projects.

For mainstream AI companies like Open AI, another sensitive topic that keeps coming up is the transparency of the data sources they have used and the way they continue to train their models, and how to fairly compensate the original owners and creators of that data.

So by being part of the UtilityNet chip-counting ecosystem, you’re not just using apps; you’re helping to make everyone’s better and safer. Plus, you get rewarded ($UNC) for your contributions. It’s a way to utilize technology and teamwork to truly change the world around us.

After all, in this AI+ era, computing is oil! More so, it’s the main underlying infrastructure for the future competitive landscape between great powers.

Ⅰ. Historical Development of Software Development

a.Development Limitations of Traditional “Hardware-Defined Software”

Ⅱ.Reverse Engineering of UtilityNet — Advantages of Software-Defined Hardware/Chips

a.Why is UtilityNet’s Core Value Based on Protocol?

b.Chips as the Core of Computing Power

c.Chip-Level Security: Portion Consistency (P Consistency)

d.POCI / Proof of Computing Integrity

Ⅲ.Realization and Optimization of Computing Power Retention and Circulation in UtilityNet

a.Differentiation: Idle Computing Power vs. Effective Computing Power

b.Performance Comparison of Different Consensus Mechanisms

Ⅳ. Summary: Building an Open, Shared Distributed Computing Power Ecosystem

Ⅰ.Historical Development of Software Development

1960s:Software engineering was recognized as an independent engineering discipline, but this period also marked a crisis in software development. Software struggled to keep pace with hardware, causing issues in the field.

1970s:The software crisis continued, with engineers attempting to reverse the situation. New ideas, languages, and hardware were introduced, initiating the rise of software engineering.

1980s:Significant changes continued as the software crisis waned. New languages and tools ushered in better engineering practices and the transition to object-oriented programming.

1990s:A flourishing decade for programming languages, with many of today’s popular languages being developed. Major changes in the industry included the rise of object-oriented programming and the emergence of the internet, introducing new development methodologies.

21st Century:With companies improving on systems established decades earlier, the focus shifted from languages and tools to methodologies aimed at making processes more customer-centric, profitable, and easier to create.

2010s:While languages and methods continued to improve, the emphasis returned to meeting software engineers’ needs, enhancing traditional software engineering education with new learning methods.

2020s:Artificial intelligence (AI) and machine learning (ML) became significant forces in software development, shaping the field’s trends.

a.Development Limitations of Traditional “Hardware-Defined Software”

Throughout the history of software development, developers have adhered to the underlying logic of “hardware-defined software” (HDS), where hardware defines drivers, which define system interfaces, and based on these interfaces, software SDKs are developed to create software. This process demands developers to maximize value within established hardware systems and platforms.

The limitations of traditional HDS include:

1. Dedicated Hardware Limitations:Many software programs were written for specific hardware platforms, limiting software portability and reusability.
2. Performance Bottlenecks:Software performance can be constrained by hardware limitations, such as early graphics processing software hindered by GPU performance.
3. Innovation Constraints:Hardware diversity and fragmentation in mobile devices require developers to write different code for various hardware configurations, hindering cross-platform application development.
4. Cost and Resources:Developing dedicated hardware often requires substantial investment and time, which small businesses and startups may find difficult to bear, limiting innovation in software development.
5. Obsolescence:Rapid technological advancements can quickly render dedicated hardware obsolete, delaying software updates to meet user needs.

With AI catalyzing the updates and iterations of both software and hardware, it is evident that the development and innovation of both are constrained. Software development is significantly restricted by hardware/chip limitations, leading to a scenario where software developers are bound by hardware-defined system programming, curtailing their creativity and imagination.

Ⅱ.UtilityNet’s Reverse Engineering — Advantages of Software-Defined Hardware/Chips

UtilityNet is a decentralized digital chip network aimed at providing chip resources for next-generation edge computing and AI infrastructure. It disrupts the traditional hardware-first logic by deriving utility from various types of chips and decentralizing the network.

Software Defined Hardware (SDH) aims to break the traditional hardware-defined software (HDS) model, making hardware more flexible to accommodate ever-changing software demands. SDH enables hardware to be reconfigurable at runtime according to software needs, unlocking developers’ innovative potential.

In this approach, UtilityNet is considered software, adopting the SDH method. The value creation process starts with a valuable token and its underlying protocol, which defines the software. The software then defines the required SDKs, followed by drivers, ultimately influencing the physical chip design.

UtilityNet SDH aims to create reconfigurable hardware and software at runtime, achieving near-ASIC performance without the costs, development time, or single-application limitations associated with ASICs. This reverse engineering process has never occurred in blockchain history, making UtilityNet’s value-driven core logic unique.

a.Why is UtilityNet’s Core Value Based on Protocol?

The core value of UtilityNet starts with the protocol, specifically the Proof of Computational Integrity (POCI), which maximizes the effective computing power of each device for users. It establishes the foundation for computing power contribution and verification, with the UNC token serving as a reward and value exchange medium for users’ computing power contributions.

POCI doesn’t rely on continuous computational tasks to maintain the network but uses the chip’s internal security engine module combined with on-chain cryptographic principles to allow the chip to self-prove its computing power. This reduces computing power loss and promotes its circulation, showcasing innovative practices distinct from most similar projects.

b.Chips as the Core of Computing Power

The protocol-defined hardware can vary widely, but defining it at the chip level is essential due to the fundamental differences between permissionless blockchain and permissioned systems, as well as distinct cryptographic requirements from tokenized centralized web3 projects. A mature, mass-produced chip often has a recognized computing power measurement standard. From a shared economy perspective, as long as the contributed computing power can be verified on-chain, the user can be rewarded with corresponding tokens. This allows the computing power to be available for rent to those in need, ensuring valuable AI computing power is efficiently transferred to customers rather than wasted on ineffective calculations for token incentives.

c.Chip-Level Security: Portion Consistency

First let’s look at Portion Consistency.The production of chips involves lithography, where EUV is projected through a mask onto a wafer coated with photoresist, etching layers to create a 3D structure. This means altering even a single transistor in an integrated circuit product is impossible, ensuring that a portion and the whole of an IC have consistent security. This is crucial for physically proving and cryptographically defining the entire proof process, allowing the validation of the entire integrated circuit by proving a portion of the chip.

It defines how a physical capability is fair game for the masses, through the IC and benchmark testing of the chip, thus giving a physical chip a certification of capability.

d.Proof of Computational Integrity (PoCI)

The PoCI’s implementation logic involves defining and proving a chip’s capability through a designed portion, then transmitting this computational capability proof. UtilityNet’s security engine (SE) comprises TRNG, PKA, SPACC, and EFUSE modules.

Steps of PoCI chip verification:
1. Generate a 128-bit random number (NN)stored in EFUSE as a binary form, marking specific circuit parts as “1” and leaving “0” areas unchanged. This key (SK) is only readable by the chip driver.
2. Generate P2 and public key:TRNG generates another random number (PRIK), used by the PKA module to create a public key (PUBK). PRIK is encrypted with SK via SPACC, producing a new key (P2) and PUBK is published, while PRIK is discarded.
3. Sign information:P2 decrypts to PRIK, which signs a message digest, producing a signature (Sign).
4. Verification:Anyone can verify the signature using Sign and PUBK. If the signature is valid, it confirms the chip’s authenticity.

This decentralized RWA (Real World Assets) digital chip network allows anyone to challenge the chip’s existence, with only the chip itself being able to prove its authenticity through digital signatures.

Ⅲ.Realization and Optimization of Computing Power Retention and Circulation in UtilityNet

a.Differentiation: Idle Computing Power vs. Effective Computing Power:

UtilityNet’s PoCI mechanism aims to reduce computing power consumption during verification and mining processes, ensuring effective computing power retention and circulation by encouraging users to provide high-quality computing power. Most projects fail to redundantly preserve and circulate computing power, often consuming most of it during mining and specifying repetitive, useless tasks that do not contribute to societal progress.

b.Performance Comparison of Different Consensus Mechanisms

Comparing UtilityNet’s PoCI consensus mechanism with POW, POS, and hybrid mechanisms:

UtilityNet’s PoCI consensus mechanism reduces computing power loss, avoids ineffective calculations, and allows computing power to be retained and circulated as a verifiable and tradable resource, efficiently serving customers in need.

Ⅳ.Summary: Building an Open, Shared Distributed Computing Power Ecosystem

In this article, we explored the evolution of software development and how AI’s advancement has exposed the limitations of traditional hardware on software innovation and development. Breaking the centralized (whether software or hardware) foundational logic is necessary to fundamentally change this. UtilityNet uses the PoCI mechanism to achieve high-cost-effective computing power services from the bottom up, offering higher chip-level security for AI development, thereby constructing an open, shared distributed computing power ecosystem.

UtilityNet’s SDH/software-defined hardware/chips ensure fair and transparent incentives for users contributing computing power resources by using chip-level verification and rewarding based on chip computing power contributions. This promotes the global adoption of chips and accelerates the construction of a distributed chip network, demonstrating significant long-term feasibility.

We are thrilled to announce that the UtilityNet Phase-1 testnet is officially launched! This marks a crucial testing phase for UtilityNet, laying a solid foundation for the future mainnet launch. The Phase-1 testnet will focus on verifying the network’s stability and security while collecting user feedback to optimize system performance.

At this stage, the testnet is open to the public, providing an excellent opportunity for early involvement with UtilityNet. It is also a vital period for providing feedback and improvements for the network’s future development. We warmly invite community partners to join the PHASE-1 testnet and witness and drive significant advancements in the field of distributed computing power.

Core Priorities of the PHASE-1 Testing

During the initial phase of the PHASE-1 testnet, the UtilityNet team will concentrate on two core validations: Proof of Computing Integrity(POCI) and the WebAssembly (WASM) virtual machine.

The POCI validation will subject the miners’ computational environments and capabilities to a stringent review to ensure that the security and data consistency of the blockchain are fully safeguarded. This validation mechanism is crucial for maintaining the trust and reliability of the network.

The validation of the WASM virtual machine will involve an in-depth assessment of its performance across various hardware and software environments to ensure that execution efficiency is optimized. This will aid UtilityNet in achieving efficient computational resource allocation and task execution across different devices.

Latest Developments in the PHASE-1 Testnet

• POCI Validation: Conducting a rigorous examination of miners’ computational environments and capabilities to ensure the security and data consistency of the blockchain.
• WASM Virtual Machine Validation:Assessing the performance of WASM in diverse hardware and software environments to ensure execution efficiency.
• Node Preparation:Nodes are being prepared for private chain testing to meet the requirements for ledger chip and on-chain computation.
• Miner Support:Providing an RPC interface for chip set burning on efuse, along with a UI APP software to help miners monitor their mining and chip set operations.
• UtilityNet Wallet (Coming Soon):A wallet extension kit designed specifically for UtilityNet users, similar to MetaMask, using web3 encryption technology to protect user assets.
• UtilityNet Block Explorer (Coming Soon):The block explorer will provide users with detailed transaction information.
• Computational Resources and Devices (Coming Soon):Supporting a wide range of needs from AI to big data analysis. Private chain deployment will allow developers to freely explore customized computational solutions based on open-source code.

Basic Concept: Framework Structure

UtilityNet Testnet’s infrastructure design is aimed at providing an efficient, secure, and scalable distributed computing service. According to the official documentation, the framework structure includes the following key components:

• Node Network: Nodes serve as the foundation of the entire network, responsible for maintaining the operation and data transmission of the testnet. Each node communicates through a peer-to-peer network, ensuring the consistency and integrity of the data.
• Miner Nodes: Miner nodes participate in the testnet consensus algorithm, packaging and verifying blocks to ensure the security and immutability of transactions.
• Containerized Deployment: The system supports containerized deployment, utilizing container technologies such as Docker to enhance the convenience and efficiency of deployment and management.

Testnet Hardware Equipment Standards

Device Model: SG6–06-A32

Note: UtilityNet has been designed from the outset to ensure that miners and computing power providers can earn effective computing power by participating in chip verification to receive UNC rewards (Phase-1 Testnet environment does not generate UNC rewards). Tokens are allocated in a positive correlation based on the contribution value of computing power, thereby incentivizing the rapid construction of the UtilityNet computing power network. UtilityNet adopts its independently innovative Proof of Computing Integrity (PoCI) verification mechanism, along with specific chip requirements designed in conjunction with UtilityNet’s collaborative framework. Miners and computing power providers must purchase specific hardware devices to participate, whether in the current testnet phase or the future mainnet launch.

How can users participate in Testnet?

Please visit the official UtilityNet GitHub to view the open source code and get the deployment guide, below are the simplified deployment instructions:

• Run a Node: Click here to see the process of Node deployment in the cookbook.
• Miner depoly:click here to see the various development processes and best practices for miner depoly in the cookbook.

Conclusion

With the guidance of this article, we expect more community users and developers to successfully participate in the early construction of UtilityNet. Should you encounter any issues during the process or have any suggestions, we warmly welcome you to reach out and seek support at any time through Discord or Telegram.

We are about to embark on a new milestone — the Phase-1 Testnet is scheduled to launch in mid-May. Additionally, we will gradually unveil more details about the Phase-2 and Phase-3 Testnets.

About Phase-1 Testnet

In the first phase, our focus will be on two core validations: Proof Of Computation Integrity (POCI) and WebAssembly (WASM) virtual machine. POCI validation will rigorously check the miners’ computing environment and capabilities to ensure the security and data consistency of the blockchain. The WASM virtual machine validation will evaluate its performance in diverse hardware and software environments to ensure efficient execution.

Overall Technical Development Progress of Phase-1 Testnet

• POCI validation: Strict verification of miners’ computing environment and capabilities to ensure the security and data consistency of the blockchain.
• WASM virtual machine validation: Evaluation of WASM performance in diverse hardware and software environments to ensure efficient execution.
• UtilityNet Wallet: An extension suite of UtilityNet wallet with features similar to MetaMask, including on-chain balance scanning and transaction records. It is designed specifically for UtilityNet users, with the UNC token as the circulating currency in transactions. Protected by web3 encryption technology, users can securely store tokens, conduct transactions, or invoke smart contracts.
• UtilityNet Block Explorer: All UI designs and sketches are nearing completion, similar to Ethereum explorers, allowing users to explore detailed information about each transaction using addresses or transaction hashes. The network explorer is widely available and will soon connect to node RPC.
• Node: Nodes are ready for private chain testing, equipped with smart contracts to meet the needs of chip recording and on-chain computation. The nodes run stably and generate consistent block reports every day.
• Miner: We have packaged RPC interfaces for users to burn chipsets on efuse, obtain key pairs, and sign from the chips. Equipped with chip drivers and SDKs for cgo program invocation. Interactions with other nodes through RPC, such as querying chain status or miner basic information, uploading chip information to the chain, declaring computational ownership, etc., are ready for testing. RPC interactions with container cloud servers are still under development and not yet complete. We also provide UI APP software to help miners monitor their mining and chip operations, supported by miner backend.
• Computing resources and devices will be open to support various needs such as AI and big data analysis.
• Private chain deployment: Developers will be able to deploy private chains based on open-source code and explore customized computing solutions freely.

Phase-2 Testnet

Phase-2 Testnet is divided into two parts:

First Half: Container Cloud Testing
We will focus on testing container clouds, concentrating on verifying and optimizing their performance and stability.

Second Half: Container Cloud Open Source and Expansion
The Container Cloud will be released as an open-source project, providing richer cloud-native plugins, expanding network functionalities, and offering more customization options.

Additionally, diverse computing application scenarios will be introduced, providing miners with broader profit opportunities.

Phase-3 Testnet

• Mainnet economic model testing
• Mainnet incentive test competition

Preparation Status
The development team is working tirelessly to ensure the stability and security of the Testnet at each stage of its development, welcoming every important milestone.

Community Participation Invitation
UtilityNet encourages miners and developers to actively participate in the initial phase of testing, accelerating the progress of Phase-2 and Phase-3 through deployment and feedback.

How to Participate
For details and guides on participating in the Testnet, please stay updated on UtilityNet’s official website and social media channels.

The launch of the UtilityNet Testnet is an important step towards our vision of a decentralized digital chip network. We look forward to embarking on this exciting journey together with developers and community members.

At the conference, Terrill Tsang, Head of Technology, delivered a presentation on behalf of the team, showcasing UtilityNet’s innovative Layer 1 blockchain project to attendees. Below is the full text of his presentation:

Hello everyone,I’m Terrill Tsang from UtilityNet Asian tech team.

Due to the weather conditions in Dubai, many of my team members were not able to attend the event. As the Tech Lead for the UtilityNet Asia, I am to be here on behalf of my team to introduce a revolutionary Layer 1 blockchain — UtilityNet.

As we could see from the screen,UtilityNet is a Decentralized Digital Chipset Network.

Before we delve deeper, let’s take a moment to reflect on the history of software development on last decades. Here we introduce UtilityNet as software, in fact, we all understand that the most important thing for a permissionless blockchain is about defining protocols. So, The actual programming language of it or the implementers are less significant. This has been that case since the inception of Bitcoin.

The traditional software development follows an HDS process which is the Hardware define Software, more precisely, the hardware defines drivers, the driver defines system interfaces, the system interface defines sdks , the sdk defines the capability of the software we build, we software engineers exploit the more and more value through hardware platform.

But UtilityNet doesn’t act like that, we could see from that ,UtilityNet, starts with a valuable token and the protocol that generates it, the protocol defines the software, then defines the drivers interact with it, then defines the hardware meet that requirements. It’s totally reversed, we call it SDH , it has never been appeared in blockchain history.

This fundamental shift in logic, where virtual value drives the realworld value itself, is transformative. Let’s find out to see an example , imagine that If I have built a vacant plot for sports facilities, some one may take the place , then build football field or track on it. But if my decision is to make swimming facilities, then I must build a swimming pool at beginning so that I can swimming. It’s just like software defined hardware.

Then , Let’s address the what, why, and how of UtilityNet.

What is UtilityNet?

It is a protocol that generates tokens and powers a decentralized platform, motivating physical hardware applications and DApps within the blockchain ecosystem.

It provides chip resources for next-generation edge computing and artificial intelligence infrastructure.

The word ‘Utility’ in UtilityNet refers to the various types of chips, while ‘Net’ denotes the decentralized network.

The protocol defines the hardware, which can vary widely.And Why we need to define hardware down to the chip level? permissionless blockchains differ fundamentally from permission ones ,and have distinct cryptographic requirements different from some tokenized or centralized Web3 projects.

Let’s check out Portion Consistency, we call it P consistency. As we know, the chip manufacturing process, which uses photolithography — layer by layer etching based on projection of EUV through mask on a photoresist-coated wafer. The cross-section reveals a 3D structure, implying that altering even a single transistor in an integrated circuit is impossible. This integral consistency is crucial for using physical chip proof in cryptography to define the entire proof process.

It defines how a physical capability is fairly recognized by the public through IC chips and benchmark tests, thereby certifying the capability of a physical chip.

UtilityNet uses two theoretical bases to establish PoCI consensus — Proof Of Computation Integrity.

PoCI moves away from the PoW concept to verify chip capabilities, allowing the capabilities of chips to be preserved and leased. Tokens incentivize providers to deploy chips, which in turn enables users needing computational power to rent these capabilities.

Now, let’s examine the logic behind PoCI implementation, focusing on certifying a chip’s capabilities through computational conduction properties.

First of all, the chip proves itself this thing, need the chip to have the knowledge that can prove itself, it comes from the true random number generator, through the intrinsic mechanism, will be generated for symmetric encryption of the key and the private key used in digital signatures, and the use of symmetric encryption of the private key encrypted, and then export the results to the chip’s pins, so that the operating system is able to get encrypted private key through the definition of the driver, and encryption of the private key of the key The key of the encrypted private key is physically burned in the EFUSE area of the chip, which can only be read and written by the symmetric encryption unit at one time, and its physical principle is similar to a special four-direction energized transistor, where energizing the transistor in one direction will break down and burn the transistor itself, so that it can read out the binary 0 or else read out the 1 in the other direction, and we then uplink the encrypted private key and the public key generated by the private key through the asymmetric physical acceleration unit, and the key is then encrypted and written to the chip. Then we will encrypt the private key and the private key through the asymmetric physical acceleration unit to generate the public key on the chain, which becomes the chip’s address on the chain, and then any challenger can challenge the authenticity of the existence of the chip, but only this chip body in the world can use the digital signature to prove itself, which is why UtlityNet is called the Digital Chip Network, which is a kind of decentralized Real World Assets.

Almost all tokens are distributed to miners, offering an unmatched level of decentralization akin to Bitcoin, making it a retro public chain.

Why proceed in this manner?

I hold a chip that meets the current BDC — Blockchain Defined Chipset standard. It’s an AI chip made of TPUs, capable of performing inference tasks on trained AI models.

With UtilityNet, this chip becomes part of a digital chipset, enabled by UNC tokens to facilitate extensive deployment and cost-effective applications. Currently, UtilityNet has evolved into a vast AI computing network, with the BDC protocol open for more chip integrations in the future.

Why are chip resources on UtilityNet more affordable? Miners can simultaneously mine and offer P2P leasing, reducing costs compared to centralized infrastructures like AWS and Google Cloud.

What tools does UtilityNet employ to serve the world?

Through the deployment of an open-source mining side container cloud suite, any miner can easily become a professional P2P cloud service provider.

Integration with more DApps alongside centralized review mechanisms ensures a healthy ecosystem.

Currently, the code is nearly fully open-sourced, and we are welcoming the Talos Age, the initial phase testnet, where you can fully engage with UtilityNet’s capabilities through the Explorer, Ai-dev platform, and Dapp-dev plugins.

Here is the professional container cloud user interface, offering extensive functionalities for current AI developers.

Developers can easily utilize this BDC chip within the container cloud to run code and tests in JupiterLab projects.

All BDC chips can be explored through the blockchain explorer.

Developers can create more DApps using browser plugins and SDKs.

DApps also unlock new DeFi play styles through on-chain chip circulation, enabling chip loans and pledges. This is the additional business potential brought about by decentralized Real World Assets.

Finally, I invite you to follow our work at X and offer special thanks to our close partner, Carmen from CoinW. Thank you all for your attention.

We are thrilled to announce that UtilityNet has officially entered the first phase of the Talos Age testnet! In this significant milestone, we have completed the development of the first phase of the code and have open-sourced it on our official GitHub for the community members and developers to use and contribute to.

Since our release on GitHub, UtilityNet development members have completed over 182 code deployments. We have had over 143 contributors participating from around the world, and our GitHub code repository has been starred by over 113 users.

GitHub: https://github.com/utnet-org/utility-readonly

I. Open Source of Testnet Code — Building the Future Together
We believe in the power of open-sourcing the testnet code at this stage. It can foster innovation, enhance transparency, and encourage broader ecosystem building and collaboration. This marks further development and openness of the UtilityNet ecosystem, allowing developers and community members to gain deeper insights into the technical architecture and implementation details of UtilityNet. The open-source code will include the implementation of core functionalities, smart contract writing, and network communication handling, among other key aspects. Your participation and feedback are crucial to us, as they will help us build a more robust and efficient global decentralized digital chip network.

II. Test Node Deployment Documentation — Your Participation is Vital
To support developers and node operators, we have also released detailed documentation for driving UtilityNet test nodes. These documents will provide you with the necessary guidance to help you quickly deploy and manage your nodes, ensuring that you can familiarize yourself with and easily contribute to the core strength of UtilityNet in this phase.

Therefore, we encourage developers and community members worldwide to actively participate in the testnet node deployment plan, helping us jointly build and improve the UtilityNet — Talos Age testnet. You will have the opportunity to gain partial equity and rewards in UtilityNet after its official launch, so don’t miss out on every opportunity to contribute to the future of UtilityNet!

III. Participation and Contribution
We cordially invite you to join our open-source community and participate in the development of UtilityNet. Whether you are a code contributor, documentation writer, key opinion leader, or node testing user, we welcome the active participation of every partner. Each of your contributions will drive UtilityNet forward, allowing us to witness the arrival of a new era together.

IV. Stay Tuned
To get more information about UtilityNet, including the latest updates, tutorials, events, and announcements, be sure to follow our official channels. We will share the latest progress through these channels and provide support and assistance.

Thank you for your support and trust in UtilityNet. Let’s work together to create the future and embark on a new chapter of decentralized computing!

If you have any questions or need further information, feel free to reach out to us via Discord — Ticket for support.

— — UtilityNet

#UtilityNet features a fully matured economic model. It is divided into four ages: Talos Age, Vajra Age, Golem Age, and Maria Age. Each age holds great significance and mission. By advancing through these ages, UtilityNet aims to establish a complete ecosystem, driving it to become a powerful decentralized global digital chip network.

The Phase 1 code of the Talos Age testnet will be open-sourced from March 28th to April 5th. This marks further development and openness of the UtilityNet ecosystem, allowing developers and community members to gain deeper insights into the technical architecture and implementation details of UtilityNet. The open-source code will include key components such as core functionality, smart contract development, and network communication handling. We will provide detailed information and guides on GitHub once the code is fully open-source, facilitating developers’ understanding and participation in ecosystem building.

Additionally, we are actively recruiting testnet nodes worldwide to assist in testing UtilityNet during this phase. Users who meet the device requirements are welcome to participate in our exclusive beta testing program. As a testnet node, you’ll have the opportunity to receive partial UtilityNet rights and rewards while helping us build and improve the UtilityNet — Talos Age testnet. Don’t miss out on every opportunity to shape the future of UtilityNet!

Testing objectives:

Validate the stability, functional completeness, and security of the UtilityNet Talos Age Phase 1 network, laying a solid foundation for the transition to the Vajra Age Phase 2.

Participation period: Talos Age testnet Phase 1.

During the first phase of the Talos Age testnet, selection of participating test nodes will be based on various factors, including online status. The selected test nodes will have the opportunity to participate in UtilityNet DAO community governance.

The main selection criteria are as follows:

Stability and reliability: Test nodes should be able to run reliably and provide stable connections and services. Node stability is crucial for ensuring the smooth operation and data transmission of the network.

Bandwidth and latency: Test nodes should have high bandwidth and low latency to ensure fast and efficient data transmission. This is essential for network performance and response time.

Resource configuration: Test nodes need to have sufficient computing resources and storage capacity to support the network’s operation and execute testing tasks. Node resource configuration should meet the expected workload requirements.

Security: Test nodes should have robust security measures to protect the confidentiality and integrity of the network and data. Node operators should follow best security practices and promptly perform security updates and vulnerability fixes.

Feedback and collaboration: Test node operators should actively participate in testing activities, providing timely feedback on network performance, issues, and suggestions. They should demonstrate good collaboration skills and effectively communicate and cooperate with other test node operators and team members.

Community engagement: Test node operators actively engage in UtilityNet community activities and discussions, contributing valuable inputs to the network’s development and improvement. They can share experiences, raise questions, and collaboratively explore and solve challenges with other community members.

Please stay tuned to the official UtilityNet website and our social media channels for more updates.

If you have any questions or need further information, feel free to reach out to us via Discord — Ticket for support.

Kubernetes, also known as K8s, is an open-source container orchestration system for automating the deployment, scaling, and management of containerized applications. It was designed and open-sourced by Google, and is now maintained by the Cloud Native Computing Foundation (CNCF).

The main features of Kubernetes include:

• Automatic bin packing: Automatically places containers based on their resource requirements and other constraints, without the need for manual scheduling.
• Self-healing: When containers fail, they are restarted; when nodes die, the containers are removed from the node and rescheduled.
• Horizontal scaling: Applications can be easily scaled using a simple command or automatically based on CPU usage.
• Service discovery and load balancing: There’s no need to modify applications to use an unfamiliar service discovery mechanism, as Kubernetes provides its own DNS server and other discovery mechanisms.
• Automated rollouts and rollbacks: Kubernetes can roll out and roll back new versions of an application following a predefined process.

These are just some of the features of Kubernetes; it has many other capabilities and features, making it the tool of choice for managing containerized applications.

Distributed AI compute networks typically involve distributing large computational tasks across multiple compute nodes spread geographically. In this context, Kubernetes (K8s) can play a vital role.

1. Automated Deployment and Scaling: AI applications often require substantial computational resources, and Kubernetes can automate the deployment and scaling of containerized applications. This means AI services can be quickly and automatically scaled up or down based on demand.
2. Load Balancing and Service Discovery: In large-scale distributed environments, Kubernetes can help automatically distribute tasks among multiple nodes to ensure load balancing. It also provides service discovery, allowing services to find each other.
3. Resiliency and Self-Healing: In a distributed environment, nodes might fail. Kubernetes is self-healing, so if a node fails, it automatically reschedules tasks to other nodes to ensure uninterrupted service.
4. Resource Optimization: Kubernetes’ resource management and scheduling capabilities can help optimize the use of hardware resources, increasing computational efficiency. This is particularly important for AI tasks, which typically require substantial computational resources.

Therefore, Kubernetes can help build and manage UtilityNet, enabling it to run more efficiently and reliably.

1.POCI (Proof of Computation Integrity)

Computational consensus is an important mechanism in blockchain technology. Proof of Work(PoW)is one of the commonly used consensus algorithms by proving one’s contribution by consuming a large amount of computing resources. PoW, however, has drawbacks such as consuming large amounts of energy and computing resources. Some new consensus algorithms such as Proof of Stake(PoS), Proof of Authority(PoA), etc. have emerged in recent years.

Nowdays, we will provide a new proof of computation integrity mechanism: Proof of Computation Integrity (PoCI). The proof mechanism completely abandons the traditional computing model and replaces it with the chip computation ownership model. In our Utility network chain, high-performance Sophon TPU computational chips are utilized for mining and AI training services in the future.

What the most important of this chip is the ”secure key”, which is a 128-bit AES code as the ”secret identity” for each TPU chip. The secure key can be sent to do cryptological calculation.On the other hand, it allows signature by private key and verification by public key. Users with the private-public key pairs based on AES are able to claim its ownership of the chip, further for computational power verification. Noted that due to the reliablility of AES algorithm, a wrong or void chip fails to give the correct keys, thus the verification of the chip ownership will be faileds, therefore the confidentiality is guaranteed.

In other words, users that obtains or possesses the chip can claim ownership of the chip’s computational power by POCI, without having to perform high-powered mathematical calculations to prove the computational power.

2.Computing Availability over Time (CAT)

According to the core idea of POCI. For a node, if it claims to have obtained N chips, then according to the principle above, it will accept N times signatures to verify POCI, which is obviously a bit tedious. We recommend an integration optimization to integrate N-time signature into a one-time signature. Once it is verified, it is proved that this node has gained the N computational power. If the total computational power of the current network is C, then the ratio η of θ to the total network computational power is:

η = Nφ/C

This is the computational power under POCI.

The computational power of each node will be serialized into segments, and the computational power of a chip is counted as a unit segment. Nφ is abstractly sliced into N segments and labeled with serial numbers. A total segment consists of 1, 2, … , n nodes form a total segment, with the length of the segment obtained by each node depends on the computational power size. And by applying VRF (Verififiable RandomFunction) function, the total fragment is random sampled at certain time interval to get the serial number, then the node corresponding to the fragment ofthe chip serial number searched is the burst block node, This mechanism shows that the node fragment with large computational power occupies more space and has a higher probability η of being chosen by VRF(Verifiable Random Function), thus achieving POCI.

However, in order to incentivize nodes to maintain their computational power, nodes that obtain the right to burst blocks need to perform CAT verifification, which repeats the POCI challenge, to prove from time to time that they are in a highly computational power state. Similarly, the digital signature of the computational chip and the verification session of each node are performed again. In this way, POCI computational proof and CAT complete the implementation of the POCI mechanism of the entire Utility network in a low-energy, low-cost and high-effificiency way.