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ICML
Faster Activation Functions at the Edge for Post-Training Speedups
Anton Lydike, Jun Bi, Jackson Woodruff
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ASPLOS
The Configuration Wall: Characterization and Elimination of Accelerator Configuration Overhead
Josse Van Delm, Anton Lydike, Joren Dumoulin, Jonas Crols, Xiaoling Yi, Ryan Antonio, Jackson Woodruff, Tobias Grosser, Marian Verhelst
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ASPLOS
An MLIR Lowering Pipeline for Stencils at Wafer-Scale
Nicolai Stawinoga, David Katz, Anton Lydike, Justs Zarins, Nick Brown, George Bisbas, Tobias Grosser
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CGO
A Multi-Level Compiler Backend for Accelerated Micro-Kernels Targeting RISC-V ISA Extensions
Alexandre Lopoukhine, Federico Ficarelli, Christos Vasiladiotis, Anton Lydike, Josse Van Delm, Alban Dutilleul, Luca Benini, Marian Verhelst, Tobias Grosser
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ASPLOS
A shared compilation stack for distributed-memory parallelism in stencil DSLs
George Bisbas, Anton Lydike, Emilien Bauer, Nick Brown, Mathieu Fehr, Lawrence Mitchell, Gabriel Rodriguez-Canal, Maurice Jamieson, Paul H. J. Kelly, Michel Steuwer, Tobias Grosser
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SC-W'23
Stencil-HMLS: A multi-layered approach to the automatic optimisation of stencil codes on FPGA
Gabriel Rodriguez-Canal, Nick Brown, Maurice Jamieson, Emilien Bauer, Anton Lydike, Tobias Grosser
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SC-W'23
Fortran performance optimisation and auto-parallelisation by leveraging MLIR-based domain specific abstractions in Flang
Nick Brown, Maurice Jamieson, Anton Lydike, Emilien Bauer, Tobias Grosser