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Add MSA and f16 inline ASM support for MIPS - #160851

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Add MSA and f16 inline ASM support for MIPS#160851
beetrees wants to merge 1 commit into
rust-lang:mainfrom
beetrees:f16-inline-asm-mips

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@beetrees beetrees commented Aug 10, 2026 •
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This PR adds vector register support for MIPS inline ASM when using the MSA extension (MSA specification), as well as adding support for the f16 type.

Ping target maintainers of MIPS targets: @Itus-Shield @Gelbpunkt @ayrtonm @LukasWoodtli @wzssyqa @chenx97 @709924470 @Cyanoxygen @Fearyncess

Tracking issues:
f16 inline ASM: #125398 (part of #116909)
MIPS inline ASM: #93335
MIPS target features: #150253

@rustbot rustbot added A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. T-compiler Relevant to the compiler team, which will review and decide on the PR/issue. labels Aug 10, 2026
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rustbot commented Aug 10, 2026

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r? @JohnTitor

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@beetrees beetrees mentioned this pull request Aug 10, 2026
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beetrees force-pushed the f16-inline-asm-mips branch from ce8eb57 to 592a2ea Compare August 10, 2026 12:14
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rustc_codegen_gcc is developed in its own repository. If possible, consider making this change to rust-lang/rustc_codegen_gcc instead.

cc @antoyo, @GuillaumeGomez

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beetrees force-pushed the f16-inline-asm-mips branch from 592a2ea to f8f3913 Compare August 10, 2026 14:38
@folkertdev folkertdev mentioned this pull request Aug 11, 2026
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folkertdev requested changes Aug 12, 2026
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r? me

Looks good overall, some small things. I'd like to hear from the target maintainers too.

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Comment thread compiler/rustc_target/src/asm/mips.rs Outdated
}
$(Self::$field)|* => {
cb(Self::$full);
cb(self);

@folkertdev folkertdev Aug 12, 2026

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what does this do? it seems to say that a register overlaps with itself?

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Hmm apparently we're a bit inconsistent here, some of the macros do include the field itself, others don't seem to.

@beetrees beetrees Aug 13, 2026

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I think having the cb(self) separate from the macro is more readable, so I've changed it to use that here.

Comment thread compiler/rustc_target/src/asm/mips.rs
Comment thread tests/assembly-llvm/asm/mips-types.rs
Comment thread tests/assembly-llvm/asm/mips-types.rs
@rustbot rustbot assigned folkertdev and unassigned JohnTitor Aug 12, 2026
@rustbot rustbot added S-waiting-on-author Status: This is awaiting some action (such as code changes or more information) from the author. and removed S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. labels Aug 12, 2026
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Reminder, once the PR becomes ready for a review, use @rustbot ready.

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beetrees force-pushed the f16-inline-asm-mips branch from f8f3913 to 5113ee9 Compare August 13, 2026 17:48
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@rustbot ready

@rustbot rustbot added S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. and removed S-waiting-on-author Status: This is awaiting some action (such as code changes or more information) from the author. labels Aug 13, 2026
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A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.

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