https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1681094/tlv320aic3120-tlv320aic3120-has-white-noise-generating-internally-on-microphone-input/6485049Wed, 16 Sep 2026 08:06:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:bf61cdc2-e6fd-4756-9b4d-3ec85b76cb76George WorkmanHi Jeff, I've been trying to attached our setup code but the website isn't wanting to take it - do you have an email address that I'd be able to share it with you? Kind regardshttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1682619/tas5830-tas5830-ppc-tools-request/6485048Wed, 16 Sep 2026 08:05:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:22fb7878-86c0-4da6-9fa8-8e1396035fb5Shenghao DingHi Guy Pls follow this link( (+) TAS5830: PPC3 (PURE PATH CONSOLE) Install SW - Audio forum - Audio - TI E2E support forums ) to submit your request. Our marketing guys will review yur request shortly.https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1671708/ucc28950-regarding-the-specifications-of-the-ucc27714evm-551-evaluation-board/6485044Wed, 16 Sep 2026 08:03:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e56803c7-ac80-4fd3-89a7-3d8b6be7eee9Anil KumarHi Kyohei, Sorry for delay, as I was out of office for past 5 days, I'll review and will respond back as soon as possible, positively by tomorrow. Regards, Anilhttps://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1682071/tps562246-tps562246-acp-constant/6485042Wed, 16 Sep 2026 08:02:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:26fe2670-e2a7-4ea7-94a3-c81a05da797dAlla UshasriHi Shawn, My calculations have it 1/Acp so its 3 here. This is DCAP3 device generally DCAP2 devices Acp would be high. Regards, Usha.https://e2e.ti.com/support/motor-drivers-group/motor-drivers/f/motor-drivers-forum/1680109/drv8343h-q1evm-bldc-output-is-dc-not-ac/6485043Wed, 16 Sep 2026 08:02:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:a0a54f3f-ab73-4ce1-990a-a95faba18536Phillip BothmaChanged it to match orientation of datasheet example. Hopefully closer to the optimised one.https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1681924/tda4vm-tda4vm-multi-cam-application---8m-camera-2ch-not-capturing/6485041Wed, 16 Sep 2026 08:01:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5a717326-0bd3-434c-bae1-5c830bb210ddKIBEOM KODear Jared McArthur, There was an issue with the power input to one of the cameras due to a HW configuration problem. The 2 channel camera is working well. Display is also working well. I have one question. According to the TDA4VM specifications, up to two channels are supported for 3840x2160@30fps(raw12). However, even when increasing the CSI clock to the 2000-2500 range, frames are not received correctly. input is intermittent, and the frames are corrupted. It operates normally when the sensor frame rate is reduced from 30 to 20 and the CSI clock is set to 2000Mbps. Why do frame drops and visual artifacts occur even though the specifications should support it? BRhttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1680850/f29h850tu-i-wrote-the-seccfg-and-i-am-not-able-to-download-anything-anymore-the-downloaded-software-is-running-fine/6485040Wed, 16 Sep 2026 08:00:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:34934a13-463b-40ce-b539-d018a8d86e55Ronan DANIOUXHello Hu, Thank you for your answer. This was the missing piece to have a complete view of how to handle SECCFG. Thank you also Zackary for the previous answers.https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1682366/am620-q1-information-on-fabrication-technology-used/6485039Wed, 16 Sep 2026 08:00:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5eba5dfd-2910-403b-a4a9-c97d09883b31Rahulsai ParthasarathyHi Sreenivasa, We are seeking this information for performing Single Event Effect analysis. Like we need info on technology used like CMOS or any other nm technology used for fabrication . Regards, Rahulhttps://e2e.ti.com/support/isolation-group/isolation/f/isolation-forum/1682461/isow1044-availabilty/6485036Wed, 16 Sep 2026 07:55:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:17296590-b85b-4c37-8fad-f61a9200348bfudong chenThreod Systems?https://e2e.ti.com/support/motor-drivers-group/motor-drivers/f/motor-drivers-forum/1681085/drv8353-drv8353s-question-about-gain-setting-for-shunt-amplifier/6485034Wed, 16 Sep 2026 07:54:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b0c672a9-a07e-4e06-bcf9-408294788caaAustin DoHi Jesus, Everything is clear for me. Thanks for the detailed explanation. Best Regards, Austinhttps://e2e.ti.com/support/sensors-group/sensors/f/sensors-forum/1681771/awr2243boost-mmwave-studio-3-1-4-4-fw-downloading-issue/6485031Wed, 16 Sep 2026 07:52:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2d2371f2-b589-4108-92ea-ee0c1bf3ae5dShane ChangHi Ahanaf, It works now with your recommended studio version. Question, how do I open the RadarStudio PostProcess GUI window for visualization? Thanks, Shanehttps://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1681353/rm57l843-accessing-spnu578-spnu579/6485027Wed, 16 Sep 2026 07:48:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5bc98825-c57e-4cd9-8668-9a7fbcfafdebjagadish gundavarapuHi stomp , Need one more daytime to provide you an update because i am checking this one internally. -- Thanks & regards, Jagadish.https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1678249/ads1000-q1-conversion-time-just-after-the-register-settings-change/6485023Wed, 16 Sep 2026 07:45:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ad06e9a9-37f8-4c4e-a276-54888b9b42d1Yoshikazu KawasakiHello Mason-san, Thank you very much for your support. Yes, your understandings are almost correct, but please let me tell you exactly what they did. Their procedure is shown below. They saw ST/BSY=0 at 9th polling which means it takes 80-90ms to get ST/BSY=0, so they thought it took around 90ms until the first conversion data becomes ready. Power up -> 93h to configuration register for single mode conversion -> 1st polling (every 10ms to confirm if ST/BSY=0, but ST/BSY=1) (I understand from your comment that the output register is ready to read out the new data even though ST/BSY=1) -> 2nd polling (ST/BSY=1) .......... -> 8th polling (ST/BSY=1) -> 9th polling (ST/BSY=0) -> Output register read It takes around 90ms to get ST/BSY=0 ONLY after configuring 93h to the configuration register because they need single mode conversion. It takes 10ms for all the following conversions. Therefore they're wondering if they can minimize that to 10ms. I understand the conversion itself finishes in 10ms even configuring 93h(single mode) for the first time after power up. I also understand it takes around 80ms to set ST/BSY=0 even though the conversion finishes in 10ms or so, so it seems there is no method to make it. Would you please tell me the followings? Do you still need timing behavior of ST/BSY and schematic? 1. The plot you sent me wasn't in good quality, so they can't see it well and asked me to take plot again with better picture quality. I'm sorry, but would you please do it again? 2. Would you please tell me the mechanism to take around 80ms(90ms at 9th polling - 10ms where the output register should be ready) to set ST/BSY=0 only when the configuration register is changed to 93h for the first time after power up? 3. Can my customer go to the next conversion without waiting for ST/BSY=0? I mean can they do this? If they can, will ST/BSY=0 be expected in 10ms? Power up -> 93h to configuration register for single mode conversion -> wait time of 10ms -> polling (ST/BSY=1) -> read out the output register(the conversion result should be ready) -> go to the next conversion even if ST/BSY=1? -> wait time of 10ms and see if ST/BSY=0? Best Regards, Yoshikazu Kawasakihttps://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1682665/mspm0g3218-q1-technical-feasibility-confirmation-dma-driven-software-pwm-with-dynamic-timer-compare-update-on-mspm0g3218Wed, 16 Sep 2026 07:44:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9d30154f-a6cd-4d1a-956e-9d1be9d816ceHoc NguyenPart Number: MSPM0G3218-Q1 Other Parts Discussed in Thread: MSPM0G3218 Dear TI Technical Support, We are evaluating the MSPM0G3218 for a software-PWM implementation using one timer and DMA. Our application requires: - 10 independent PWM output channels - PWM frequency: 400 Hz - PWM period: 2.5 ms - Duty-cycle resolution: 0.01% - Common PWM phase for all channels - GPIO outputs may be distributed over one or two GPIO ports - The CPU should not execute an ISR at every PWM edge - The PWM waveform should be generated autonomously by the timer and DMA At 400 Hz, a 0.01% duty-cycle resolution corresponds to: - 0.25 us time resolution - 10,000 timer counts per PWM period For the prototype, we are considering a 10 MHz timer clock: - Timer tick: 100 ns - PWM period: 25,000 timer counts - 0.01% resolution is therefore achievable The proposed architecture is: 1. A TIMA0 zero event starts a new PWM period. 2. DMA writes a GPIO DOUTSET mask to set all active PWM outputs. 3. A timer compare event triggers DMA. 4. The DMA writes the corresponding GPIO DOUTCLR mask to turn off outputs whose duty cycle expires. 5. The same compare event also triggers another DMA channel which writes the next compare timestamp into the timer compare register. 6. The next compare event then repeats the sequence until all falling edges in the current PWM period have been processed. 7. At the next zero event, the sequence starts again. Conceptually, the sequence is: TIMA0 ZERO -> DMA write GPIO DOUTSET TIMA0 CC0 event -> DMA write GPIO DOUTCLR -> DMA write next CC0 compare value -> next TIMA0 CC0 event For two GPIO ports, the proposed DMA allocation is: DMA 1: TIMA0 ZERO -> GPIOA DOUTSET DMA 2: TIMA0 ZERO -> GPIOB DOUTSET DMA 3: TIMA0 CC0 -> GPIOA DOUTCLR DMA 4: TIMA0 CC0 -> GPIOB DOUTCLR DMA 5: TIMA0 CC0 -> TIMA0 CC0 compare register If all PWM pins are located on one GPIO port, the required number of DMA channels could be reduced. The event routing would use the timer event publisher, the event fabric, and the DMA generic subscriber input. The GPIO output would use the atomic DOUTSET31_0 and DOUTCLR31_0 registers. We would like TI to confirm the following points: 1. Can a TIMA0 compare event be routed through the event fabric to trigger one or more DMA channels repeatedly during the same PWM period? 2. Can one DMA channel write a new value to the TIMA0 CC0 compare register on every CC0 event, with source address incrementing through an array of compare timestamps and destination address fixed to the CC0 register? 3. Does a write to the CC0 register with: GPTIMER_CCCTL_CCUPD_IMMEDIATELY take effect soon enough to generate the next compare event in the same timer period? 4. Is it permitted to write the same compare register from DMA that generated the DMA trigger? 5. If the current compare event occurs at timer count N and DMA writes a new compare value M, what restrictions apply to M? In particular: - Must M always be greater than N? - What is the minimum safe difference M - N? - Can two consecutive compare events be separated by only a few timer clock cycles? - What happens if the next compare value is already behind the current counter value? 6. If GPIO clear DMA and compare-register DMA are triggered by the same timer event, is the ordering deterministic? We need to know whether the GPIO clear transfer is guaranteed to occur before or after the compare-register update transfer, or whether software must use separate event channels. 7. Can multiple DMA channels be triggered by the same timer event without losing an event or causing a DMA request-overrun? 8. Does the DMA support repeated transfer sequences with: - source address increment - fixed destination address - automatic transfer count decrement - automatic reload at the beginning of the next PWM period - optional linked-list or descriptor chaining 9. Is there any restriction on DMA writes to: - GPIO DOUTSET31_0 - GPIO DOUTCLR31_0 - TIMA0 CC0/CC1 compare registers 10. Which exact TIMA0 event publisher ID and DMA subscriber configuration should be used for: - TIMA0 zero event - TIMA0 compare-up event CCU0 - TIMA0 compare-down event CCD0 11. Is the DMA trigger path from TIMA0 through the event fabric deterministic with respect to latency and jitter? 12. What is the worst-case latency from the timer compare event to: - GPIO DOUTCLR write - CC0 compare-register write 13. What is the minimum guaranteed time between two DMA-triggered compare events at a 10 MHz timer clock? 14. Is there an official TI example, SDK example, application note, or reference implementation showing: - timer compare event triggering DMA - DMA writing the next timer compare value - repeated same-period compare-event chaining - DMA writing GPIO set/clear registers 15. If writing CC0 from DMA on the same CC0 event is not supported or not guaranteed, what is the recommended TI architecture for this use case? Possible alternatives would be: - DMA plus a timer compare ISR that schedules the next edge - multiple timer compare channels - use of a timer repetition counter - use of a different timer mode - use of a second timer - use of a hardware PWM channel per output For reference, the expected PWM schedule contains at most 10 unique falling edges per PWM period. Equal duty cycles are combined into a single edge mask. The CPU-side data structure would be similar to: typedef struct { uint16_t edgeTick; uint32_t clearMaskA; uint32_t clearMaskB; } PwmEdge_t; typedef struct { uint32_t setMaskA; uint32_t setMaskB; uint8_t edgeCount; PwmEdge_t edge[10]; } PwmFrame_t; The RAM requirement is expected to be approximately: - One frame buffer: about 132 bytes for two GPIO ports - Double buffer: about 264 bytes - Additional DMA control state: approximately 30 to 80 bytes The RAM estimate assumes that the waveform is represented as edge timestamps and GPIO masks. We do not intend to store 10,000 waveform samples per channel. Please confirm whether the fully autonomous DMA event-chain implementation is supported and provide the exact register configuration or a minimal code example if possible. Best regards, HocMSPM0G3218MSPM0G3218-Q1https://e2e.ti.com/support/site-support-group/site-support/f/site-support-forum/1682015/am261-som-evm-am261x-required-sysconfig-and-ospi-register-settings-for-octal-ddr-psram-with-phy-mode-enabled/6485012Wed, 16 Sep 2026 07:37:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:df08f345-93a6-4ed9-b48f-f13962dcda4eLakshya VermaHi Hiroshi, Let me check this, I will get back to youhttps://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1682664/am2434-overcurrent-detection-sdfm-using-fast-detectWed, 16 Sep 2026 07:36:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d217ffa8-9dcd-4c18-b57d-84894b05a5d2Christian DevPart Number: AM2434 Hello, currently 'Fast Detect' for overcurrent detection is not working in my project. The description and functionality are understood as follows. Window Size: The section of the bitstream being looked at; Zero Count Max Threshold: The maximum allowed number of zeros in the window; Zero Count Min Threshold: The minimum allowed number of zeros in the window. When detecting overcurrent with the comparator, the SINC filter order and the OSR specify the value range (e.g. SINC3, OSR of 64 -> 262144), with a value of zero amperes lying exactly in the middle (131072). For 'Fast Detect', I would therefore have concluded, that zero amperes would be correspond to 10, for a window size of 20 samples (Modulator should provide a 50/50 Bitstream). To define symmetrical limits centered around zero, the Zero Count Max Threshold and Zero Count Min Threshold should be 11 and 9. Is this correct? Assuming my hardware is designed for a range of +/- 50, +50A should be a continous 1 bitstream, and -50A a continous 0 bitstream. With the previously defined limits of 11/9, wouldn't Fast Detect then trigger over a range of +/-5 A? Is that correct, or am I misunderstanding something? Besides the basic functionality, another thing I'm curious about is whether any additional configuration is required. I want to use the trip events trip_e3_0 through trip_e3_2 to disable the EPWM. Since I've already used the 'Comparator' for overcurrent detection, the corresponding PRUICSS_PWM_TZ_OUT is configured (and successfully working). For 'Fast Detect' only the API function SDFM_configFastDetect() is used for configuration and enabling, as shown in the examples. Is anything else required besides this? Best regards, ChristianIndustrial AutomationAM2434https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1682419/tps923655-issue-designing-input-filter/6485010Wed, 16 Sep 2026 07:31:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:83808b42-e509-4475-94ff-f7349f1ad822Lucia GaoDear Sir, Let me check and get back to you soon. Thank you! BRs Luciahttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1682622/tmux1308-q1-d-output-pin-to-the-mcu-adc-port-question/6485008Wed, 16 Sep 2026 07:29:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:071c5b67-c8a6-4248-969f-770c8dd8bd3fClemens LadischThe TMUX1308-Q1 itself does not care. How to design a filter depends on the ADC. Note that the TMUX has a resistance and capacitance; see the R ON and C DON specifications.https://e2e.ti.com/support/dlp-products-group/dlp/f/dlp-products-forum/1672242/dlplcr4500evm-the-image-projected-by-the-dlp4500-has-a-lot-of-white-spots/6485007Wed, 16 Sep 2026 07:29:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0c765421-2115-449a-b86d-bb42f7557492yanjie LiHi Aaron, Thank you for confirming this with the customer support team. Could you please advise me on the next steps for the warranty replacement/RMA process? Please let me know if I need to provide any additional information or documentation. Thanks again for your help. Best regards, Yanjie Lihttps://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1682662/msp430fr6043-fram-data-is-erased-even-though-it-is-protectedWed, 16 Sep 2026 07:24:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2c59ca06-7168-463f-a9d5-380b997467b9Analogics Rnd SolarPart Number: MSP430FR6043 Hi TI Team, I hope you are doing well. I am using the MSP430FR6043 controller, and I want to store 300 bytes of data in FRAM. I can successfully write to and read from the FRAM during normal operation. when I program new firmware, the FRAM data is erased, even though I have enabled the FRAM write protection. In Code Composer Studio (CCS), the default programming setting is "erase Main memory" I do not want to change this setting. Could you please suggest a suitable method to store 300 bytes of data in FRAM. the writing address frm 0x6E00 thank you Best regards Veerannamsp430fr6043Test & Measurement