Ian Howson

The firmware isn’t the brain. It’s the lifeline. You can recover from a bad UI. You can fix a mechanical tolerance post-DVT. But bad firmware? That’s a 𝐩𝐫𝐨𝐝𝐮𝐜𝐭 𝐫𝐞𝐜𝐚𝐥𝐥, a 483 warning, or worse—a critical incident logged in vigilance databases across the EU. Yet we still see embedded teams treating MedTech firmware like it’s running a smartwatch. On a Reality check, we found: – A missed watchdog trigger in a patient monitor isn’t a glitch. It’s 𝐧𝐨𝐧-𝐜𝐨𝐦𝐩𝐥𝐢𝐚𝐧𝐜𝐞 𝐰𝐢𝐭𝐡 𝐈𝐄𝐂 𝟔𝟎𝟔𝟎𝟏-𝟏 𝐂𝐥𝐚𝐮𝐬𝐞 𝟏𝟑.𝟏. – A blocking I2C read from a sensor in an infusion device isn’t just inefficiency. It can cause a 𝐝𝐨𝐬𝐞 𝐝𝐞𝐥𝐚𝐲 — and if you're not mapping that delay to a clinical impact, you're flying blind. – Failing to implement safe-state transitions on peripheral fault detection? That’s 𝐚 𝐝𝐢𝐫𝐞𝐜𝐭 𝐯𝐢𝐨𝐥𝐚𝐭𝐢𝐨𝐧 𝐨𝐟 𝐈𝐒𝐎 𝟏𝟒𝟗𝟕𝟏 𝐫𝐢𝐬𝐤 𝐜𝐨𝐧𝐭𝐫𝐨𝐥 𝐦𝐞𝐚𝐬𝐮𝐫𝐞𝐬. This isn’t just firmware. It’s 𝐬𝐨𝐟𝐭𝐰𝐚𝐫𝐞 𝐨𝐟 𝐮𝐧𝐤𝐧𝐨𝐰𝐧 𝐩𝐫𝐨𝐯𝐞𝐧𝐚𝐧𝐜𝐞 (𝐒𝐎𝐔𝐏) unless you have: 1. Bidirectional traceability from requirement → test case 2. Risk analysis tied to each control path 3. Formal verification where failure = hazard 4. FMEA at the software module level — not just system And don’t even start with 𝐎𝐓𝐀 𝐮𝐩𝐝𝐚𝐭𝐞𝐬 unless your rollback logic has been validated in a degraded power scenario. Because in MedTech, half-upgraded firmware isn’t a bug. It’s an 𝐚𝐝𝐯𝐞𝐫𝐬𝐞 𝐞𝐯𝐞𝐧𝐭. 𝐒𝐨, 𝐰𝐡𝐚𝐭 𝐈𝐂𝐏𝐬 𝐠𝐞𝐭 𝐰𝐫𝐨𝐧𝐠? They underfund embedded early, believing clinical value lives only in the hardware. They separate QA from engineering, thinking risk can be reviewed, not designed. They delay firmware testing till after EVT, forgetting that 𝟗𝟎% 𝐨𝐟 𝐩𝐨𝐬𝐭-𝐦𝐚𝐫𝐤𝐞𝐭 𝐜𝐨𝐫𝐫𝐞𝐜𝐭𝐢𝐨𝐧𝐬 𝐬𝐭𝐞𝐦 𝐟𝐫𝐨𝐦 𝐬𝐨𝐟𝐭𝐰𝐚𝐫𝐞 𝐛𝐞𝐡𝐚𝐯𝐢𝐨𝐫 𝐮𝐧𝐝𝐞𝐫 𝐞𝐝𝐠𝐞-𝐜𝐚𝐬𝐞 𝐜𝐨𝐧𝐝𝐢𝐭𝐢𝐨𝐧𝐬. Your firmware isn’t a cost center. It’s your 𝐟𝐢𝐫𝐬𝐭 𝐥𝐢𝐧𝐞 𝐨𝐟 𝐫𝐞𝐠𝐮𝐥𝐚𝐭𝐨𝐫𝐲 𝐝𝐞𝐟𝐞𝐧𝐬𝐞 — and your last line of patient safety. If your embedded team doesn’t understand watchdog hierarchy, ADC noise floors under real-world EMI, or how to debounce clinical alarms under FDA alarm fatigue guidance… They’re not building MedTech. They’re building risk. #MedTech #Wearables #FirmwareEngineering #EmbeddedSystems #PPG #SpO2 #ECG #SignalAcquisition #BatteryOptimization #EngineeringLeadership #DigitalHealth

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Stop the LLM Hallucination Crisis in Embedded Systems: Introducing the 'Zero Hallucination' Cognitive Architecture The embedded software world—from RDK gateways to Android TV set-top boxes—is drowning in a Crisis of Complexity. Millions of lines of code, opaque vendor SDKs, and siloed build systems make traditional root cause analysis (RCA) nearly impossible. We cannot rely on probabilistic LLMs alone for mission-critical debugging; the risk of hallucination is too high. Our proposed Automated Project Understanding Framework solves this by enforcing a "Zero Hallucination" Architectural Paradigm that fundamentally transforms the role of Generative AI. 🔹 Key Innovations for Trustworthy RCA: 🔒 Decoupling Reasoning from Parsing The LLM acts as a semantic orchestrator and intent recognizer. Parsing, symbol resolution, and dependency mapping are delegated to deterministic, non-hallucinating tools like AST-analyzers and Doxygen. ✅ The "Trust but Verify" Loop Every LLM-generated hypothesis is rigorously verified against the codebase's ground truth: • Existence Check: Confirm all referenced code components exist • Path Feasibility: Use Doxygen call graphs to ensure valid execution paths • Build Configuration Validation: Verify code compilation with preprocessor definitions 🧠 7-Layer Cognitive Memory This architecture mimics a human expert's mind: • Semantic Memory: Immutable facts and vendor specifications • Episodic Memory: Past bug fixes via vector search • Spatial Memory: Graph-based mental map of project topology The framework integrates automated build forensics and ML-powered log anomaly detection to provide expert-level assistance for embedded challenges. #EmbeddedSystems #AIinEngineering #RootCauseAnalysis #LLMs #ZeroHallucination #DevOps #SoftwareDevelopment

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New technology means new attack surfaces. The rollout of AI and LLM solutions brings with it an increased need for AI security experts.

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“FLUQs: the Rangen Revision” (for Brent Rangen) is a systems manual for AI Visibility Engineers. It outlines how to detect latent stakeholder frictions (FLUQs), structure them into Signal Alignment Records (SARs), and deploy AI-reusable EchoBlocks. Built for the synthesis era, it reframes content creation as signal engineering — optimizing for compression survival, citation uptake, and ecosystem propagation.

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“Anthropic recently published a blog post about building a C compiler entirely with Claude . They called it CCC (Claude’s C Compiler) and claimed it could compile the Linux kernel. 100% of the code was written by Claude Opus 4.6, a human only guided the process by writing test cases. That sounded interesting enough to test the claim and benchmark CCC against the industry standard GCC” https://lnkd.in/gUpDEU69

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🔧 Hazard Detection Unit (HDU) for Dual-Issue Pipeline – Feedback Welcome! I started with the Hazard Detection Unit (HDU) for my dual-issue pipelined RISC-V CPU to tackle one of the most complex modules early. This way, I can continue working on the rest of the system—like the Forwarding Unit and pipeline stages—while giving myself time to reflect and refine the HDU logic if needed. To verify my HDU, I built a randomized testbench with 20,000 test cases to ensure that every possible hazard scenario shows up in the waveform. This helps me clearly observe forwarding paths, stalls, and corner cases in a controlled but exhaustive environment. 🖼️ The screenshot includes: • A waveform view with highlighted hazard detections and control logic • A hand-drawn diagram that maps all the forwarding/stalling paths between issue slots A and B • Color-coded annotations to trace hazard relationships between rd, rs1, and rs2 across pipeline stages 📌 If you notice anything incorrect in my hazard diagram or waveform logic, please let me know! Next, I’ll be implementing the Forwarding Unit, followed by the main pipeline stages and register design. #RISC_V #VHDL #FPGA #ComputerArchitecture #HazardDetection #PipelineDesign #EngineeringStudent #DualIssueCPU #HDLVerification #TestbenchDesign #verification #RTL

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🧠 Memory isn't an add-on—it's the core of any truly intelligent agent. In my upcoming blog, I dive into the actual implementation of a layered memory architecture for AI agents—designed to handle fast recall, session continuity, and long-term knowledge grounding using a triad of: 🔹 L1 – In-Memory Cache (Active Context) 🔹 L2 – Vector DB (Session Memory) 🔹 L3 – Graph DB (Knowledge Memory) This isn't just theoretical. I’ve put this into practice with real agent frameworks and explored how memory impacts performance, continuity, and contextual reasoning. From agent personalization to retrieval-aware decision making, memory is what makes agents feel less like tools—and more like intelligent collaborators. 🚀 The blog walks through each layer, how to wire them up, and the tangible benefits they unlock when combined. Stay Tuned #AI #GenAI #RAG #AgenticRAG #AIAgents

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Download Pentera Labs Report - revealing three new critical injection points in the ingress-nginx controller, building on Wiz’s IngressNightmare CVE. These overlooked vulnerabilities could let attackers hijack traffic, spoof headers, or reach unauthorized backend services - They exist in one of the most widely used ingress controllers in Kubernetes, putting countless environments at risk. This research highlights how small misconfigurations can lead to major exposure in modern cloud-native architectures. What’s Inside: ✅ 3 new injection vulnerabilities in ingress-nginx ✅ How attackers find and exploit CVEs in open source ✅ Actionable tips to secure your Kubernetes environment https://lnkd.in/eHtX6EdP

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A small C++ error with an `auto` variable declaration ended up driving me nuts for hours this week. Full details are in the article, but tl;dr - I ended up making a copy of a struct with `auto`, rather than a reference. So all that calibration data I read from the sensor didn't actually land in the place I expected. I needed `auto&` (or, even better, to not try to be clever and save some typing.) https://lnkd.in/gwN7CbBv

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The CRA recommends using SBOMs for vulnerability management. Great. Now let’s apply that to a real embedded product: - a main processor running Linux with a Yocto Project based distribution - sensor processors running Zephyr - a server backend written in Python on Linux Next step: feed all those SBOMs into a single vulnerability scanning tool. This time, DependencyTrack. And then… What could possibly go wrong? Quite a lot, actually. Find out at FOSDEM, in the "SBOM and supply chains" devroom, Sunday morning, February 1 at 9h30. https://lnkd.in/eDdB3fTw

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In autonomous vehicle design, lossy data is dangerous. If a sensor misses a signal, the system fails. In hiring, the resume is a lossy sensor. It captures titles and timelines— but misses the most important thing: your judgment. This creates what I call the Invisible Operator: The person doing exceptional work whose impact isn’t legible to the market. They’re not missing skill. They’re missing representation. At Navii, we use AI to build a higher-resolution model of professional capability: Not just what you did— but how you think, decide, prioritize, and execute. This is the shift: From “searching for jobs” to engineering trust. #AI #Hiring #CareerTech #Trust #FutureOfWork #navii

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PoC/demo demonstrating code injection via COM (using the IRundown::DoCallback() mechanism) to execute a payload in the context of a selected process, including lsass.exe (or any other PID). https://lnkd.in/d2T-synR

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HOW A HIDDEN CONGESTION ISSUE BECAME A NEW FLOORPLAN RULEBOOK 🚩 First signal Routing runtime exploded for one block. DRC count shot up only in one quadrant. Timing was ok on paper. But ECOs kept breaking that same region. 🔍 Step 1 Symptoms before tools We saw weird detours in layout screenshots. Long S shaped buses. Local nets escaping far away and coming back. Engineers were adding fixes blindly in that area. 📊 Step 2 Look at hard data We pulled global congestion maps. That strip was deep red in route guides. Track utilization above 90 in multiple layers. Pin density histogram was completely skewed for that channel. 🧭 Step 3 Correlate with design intent We overlaid macros on the congestion heatmap. All macro pins were on one edge. Three wide buses and high fanout control nets crossed the same window. No dedicated feedthrough channel existed. 🧪 Step 4 Minimal experiments We did a trial with only placement and trial route. No CTS. No optimization. Congestion hotspot was still there. So it was a floorplan and pin architecture issue. Not timing. 🛠 Step 5 From issue to solution We rotated macros to spread pins. Reserved clean channels for wide buses. Split control nets with local buffering. Rebuilt blockages using real congestion reports. 🚀 What changed Routing became predictable. Local ECOs dropped. We converted this debug into a checklist Pin spread rules Channel budgeting Pre CTS congestion signoff 💬 Your turn How do you detect congestion early before it becomes a tapeout risk Share one report or view you always check #PhysicalDesign #VLSI #ASIC #Floorplanning #RoutingCongestion #EDA #TimingClosure

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While for Robot taxis, it is almost always ok to rely on the cloud, for real level 4 systems, you are going to be able to deal with the all O.D.D locally in the car, that means, having a local map always ready to take over, a lot of regulation of traffic understanding on board that Robot taxis don't actually need, as they use data telling them the most commonly driven path for places they know very very well. Level 4 is not Robotaxi, by far, and if you understand that a Level 4 car needs to deal with unknown roads, then you understand that you are going to pile multiple systems, dedicated to solve multiple different problems that robottaxi does not meet. The multiple systems on Chip of Athos Silicon was design to solve Level 4, and many other problems that requires multiple systems to work together without steeling the performance of each other, like most SDV systems are doing with VMs. The #mSoC is the solution if you have analyzed properly the problem you got to solve for really safe ADAS. https://lnkd.in/gSnFCpbM

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