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[LSFE] Update fetch_add to add atomic floating-point operations (ARM-software#307)
Add details of atomic floating-point operations for `fetch_add`, for 16-bit, 32-bit and 64-bit floating-point types. No support for 8-bit and 128-bit types.
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‎atomicsabi64/atomicsabi64.rst‎

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@@ -217,6 +217,7 @@ changes to the content of the document for that release.
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| Issue | Date | Change |
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+=========+==============================+===================================================================+
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| 00alp0 | 5\ :sup:`th` September 2024 | Alpha Release. |
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| 00alp1 | 5\ :sup:`th` February 2025 | Added table for floating-point atomic `fetch_add` operations |
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+---------+------------------------------+-------------------------------------------------------------------+
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@@ -1061,6 +1062,97 @@ compare-exchange. The result is returned in ``X0`` and ``X1``.
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+-------------------------------------+---------------+--------------------------------------+
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32-bit floating-point types
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---------------------------
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In what follows, register ``X1`` contains the location ``loc`` and ``S1``
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contains ``val``. The value initially loaded from memory is returned in
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``S0``.
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.. table::
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+-----------------------------------------------------+--------------------------------------+
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| Atomic Operation | AArch64 |
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+=====================================+===============+======================================+
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| ``fetch_add(loc,val,relaxed)`` | ``Armv8-A`` | .. code-block:: none |
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| | | |
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| | | loop: |
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| | | LDXR W0, [X1] |
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| | | FMOV S0, W0 |
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| | | FADD S1, S1, S0 |
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| | | FMOV W0, S1 |
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| | | STXR W3, W0, [X1] |
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| | | CBNZ W3, loop |
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| +---------------+--------------------------------------+
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| | ``FEAT_LSFE`` | .. code-block:: none |
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| | | |
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| | | LDFADD S1, S0, [X1] |
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+-------------------------------------+---------------+--------------------------------------+
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| ``fetch_add(loc,val,acquire)`` | ``Armv8-A`` | .. code-block:: none |
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| | | |
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| | | loop: |
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| | | LDAXR W0, [X1] |
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| | | FMOV S0, W0 |
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| | | FADD S1, S1, S0 |
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| | | FMOV W0, S1 |
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| | | STXR W3, W0, [X1] |
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| | | CBNZ W3, loop |
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| +---------------+--------------------------------------+
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| | ``FEAT_LSFE`` | .. code-block:: none |
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| | | |
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| | | LDFADDA S1, S0, [X1] |
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+-------------------------------------+---------------+--------------------------------------+
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| ``fetch_add(loc,val,release)`` | ``Armv8-A`` | .. code-block:: none |
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| | | |
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| | | loop: |
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| | | LDXR W0, [X1] |
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| | | FMOV S0, W0 |
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| | | FADD S1, S1, S0 |
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| | | FMOV W0, S1 |
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| | | STLXR W3, W0, [X1] |
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| | | CBNZ W3, loop |
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| +---------------+--------------------------------------+
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| | ``FEAT_LSFE`` | .. code-block:: none |
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| | | |
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| | | LDFADDL S1, S0, [X1] |
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+-------------------------------------+---------------+--------------------------------------+
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| ``fetch_add(loc,val,acq_rel)`` | ``Armv8-A`` | .. code-block:: none |
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| ``fetch_add(loc,val,seq_cst)`` | | |
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| | | loop: |
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| | | LDAXR W0, [X1] |
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| | | FMOV S0, W0 |
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| | | FADD S1, S1, S0 |
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| | | FMOV W0, S1 |
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| | | STLXR W3, W0, [X1] |
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| | | CBNZ W3, loop |
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| +---------------+--------------------------------------+
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| | ``FEAT_LSFE`` | .. code-block:: none |
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| | | |
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| | | LDFADDAL S1, S0, [X1] |
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+-------------------------------------+---------------+--------------------------------------+
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8-bit floating-point types
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--------------------------
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Floating-point atomic operations not supported for 8-bit types.
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16-bit floating-point types
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---------------------------
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The mappings for 16-bit types are the same as 32-bit types except the registers
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used are ``H``-registers, and they use the ``H`` variants of instructions.
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64-bit floating-point types
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---------------------------
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The mappings for 64-bit types are the same as 32-bit types except the registers
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used are ``D``-registers and ``X``-general purpose registers.
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128-bit floating-point types
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----------------------------
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Floating-point atomic operations not supported for 128-bit types.
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Special Cases
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=============

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