ASML

For patterning the most critical layers in today’s advanced chips, chipmakers need the precision patterning of extreme ultraviolet (EUV) lithography – and they need that patterning to be fast enough to support high-volume manufacturing. With a throughput of 230 wafers per hour, 44% higher than previous systems, the TWINSCAN NXE:3800E is our highest-productivity EUV lithography system. Here are three technical advances that were key to reaching that speed: 💥A higher-power source produces more than 500 W so wafers can be exposed more quickly. 🏎️Faster wafer stages turn that higher power into faster patterning. 🏭Other metrology software solutions and improvements to the system’s mechatronics, including a new wafer handler and faster reticle stage, enable the faster exposure. And we're working hard to build our systems faster, both in the factory and in the field, and expedite delivery so our customers can meet the increased demand in today's chip market.

🚨 BREAKING: We just reported our Q1 2026 financial results! 👇 📈 Our Q1 2026 total net sales were €8.8 billion – reflecting a strong quarter for ASML business. 🤝 “The semiconductor industry's growth outlook continues to solidify, driven by ongoing AI-related infrastructure investments. In response, our customers are accelerating their capacity expansion plans for 2026 and beyond,” said ASML President and Chief Executive Officer Christophe Fouquet. “ASML's order intake continues to be very strong as a result, and we are closely aligned with our customers to support their demand in a combination of delivery of new systems and performance upgrades of their installed base.” 📊 "These business dynamics underpin our expectation that 2026 will be another growth year for all our businesses,” Fouquet said. ➡️ We expect second-quarter total net sales between €8.4 billion and €9.0 billion. We expect R&D costs of around €1.2 billion and SG&A costs of around €0.3 billion. 🔉 “Given the demand dynamics discussed above, we now expect total net sales for 2026 to be between €36 billion and €40 billion, with a gross margin between 51% and 53%," Fouquet said.

Modern chips rely on a range of materials that not only make up the semiconductor die itself, but also play critical roles in the packaging that shields them and connects them to the outside world. Here are three materials that play a key role in both the microchip circuitry and the packaging that protects it: 💪 Silicon is the foundation that chips are built on because its semiconducting properties are behind transistors’ current-switching abilities. It’s also used for large-area substrates, or interposers, in 2.5D and 3D advanced packaging. ⏳ Silicon dioxide is used to form insulating layers in microchip structures. And, because of its thermal and mechanical properties, it’s also often a primary component of the epoxy molding compound used to encapsulate chips. 🟠 Copper is used for the interconnects that serve as a chip’s wiring, carrying electrical signals to and from transistors. Its electrical and mechanical properties, valued within chips, also lead to its widespread use for chip packaging connections. Together, these essential materials help ensure modern devices meet the demands of today’s technology landscape.

What’s at the heart of every microchip powering your favorite devices? 📱 A microchip might look simple, but under the surface lies a network of complex circuitry that it needs to do what it does. Learn about the dies that carry this circuitry and their evolving role in shaping the future of electronics.

Twenty-five years ago, our prototype EUV light source produced just 1 watt (W). Now, our research teams have demonstrated a path from today's 500W to tomorrow's 1,000W. EUV lithography relies on a laser-produced plasma (LPP) source. Powerful laser pulses are fired at tiny droplets of tin travelling through a (near) vacuum, transforming the droplets into exploding balls of plasma 40 times hotter than the surface of the sun and causing them to emit an intense burst of EUV light. To create enough EUV light for making microchips, this process is repeated 60,000 times per second in our latest commercial sources. Here's why that research path to 1,000W matters to our customers: 🔬 We managed to further increase the repeat rate of our tin droplets from 60,000 to 100,000 times per second. That means we got more light out of the system, while simultaneously improving the overall energy efficiency of the system. ⚡ Higher power will directly unlock higher productivity. In 2018, hitting 250W enabled volume production at 125 wafers per hour. More EUV power means faster systems, helping customers operate more cost-efficiently. 🏭 This research milestone validates our LPP approach. A commercial 1,000W source isn't here yet, but the demonstration confirms the architecture can scale to even higher power levels in support of the roadmaps of our customers. Getting there wasn't a straight line. It took decades of incremental breakthroughs, such as re-shaping tin droplets to increase plasma efficiency, preventing laser feedback, and engineering mirrors with over 100 ultra-precise material layers. Each step unlocked the next. And that's how we keep powering technology forward with you.

🏅 We're honored to receive a Supplier Excellence Award from our long-time customer Texas Instruments for "Excellence in Production Support and Cost Reduction Initiatives". Chipmaker TI purchased their first TWINSCAN system 25 years ago. They have been building out their fleet ever since for the mass production of analog and embedded processing chips. Last year, we began a joint, data-driven initiative to evaluate and reduce the cost per pattern across all systems in their fabs. It was a significant effort by both teams, resulting in several meaningful opportunities to drive down cost. Let’s celebrate the power of teamwork and impact of data-driven collaboration in our industry! 🙌

Holistic lithography has been at the heart of what we do at ASML for more than 15 years. But what is holistic lithography, and how does it deliver value to chipmakers? Read on to learn about our approach. 👇

With continued shrink becoming more complex, chipmakers are pioneering new ways to improve chip performance. A key enabler of their innovation? Wafer bonding. By splitting device architectures over multiple silicon wafers and then bonding them together, chipmakers can enable more efficient power delivery, better signals and faster data flows. But implementing this kind of 3D integration also changes the demands of chip manufacturing. Here are 3 challenges chipmakers face when they use wafer bonding: 🔬 Overlay: Bonding wafers causes significant distortion and warping that need to be corrected for when the next layer is patterned on the bonded structure. 🎯 Alignment: To position bonded wafers for patterning, lithography systems have to detect alignment markings buried deep under existing layers. 🏭 Yield: Bonding increases the rate of patterning defects that can stop chips from working, causing lower yields. Tackling these challenges is key to maximizing throughput so chip manufacturing stays cost-efficient and chipmakers can keep innovating to push chip technology to the next level.

This week at our Global Leadership Meeting, we honored three colleagues with the Litho Legend Award, recognizing leaders whose long-term commitment has helped advance our technology, drive continuous improvement and strengthen the value we deliver to our customers: 🚀 Mark Ting for guiding EUV from early industrialization into high-volume manufacturing while building strong customer leadership and execution in Taiwan. 📈 Ron Kool for scaling DUV into a major business and establishing the BPI organization, strengthening performance across ASML. 💡 Jack Jau for pioneering key inspection innovations, including e-beam and EUV reticle defect inspection, which advanced critical metrology capabilities. Congratulations to our Litho Legends!

📢 We've reached a major milestone for High NA EUV. imec has received our TWINSCAN EXE:5200 High NA EUV lithography system, the tool with the strictest performance specifications available today, in its 300 mm cleanroom in Leuven, Belgium. Operating the High NA EUV system in direct connection with state-of-the-art metrology and patterning equipment and materials accelerates learning cycles to unlock the performance needed for sub‑2 nanometer logic and memory technologies and beyond, supporting the rapidly scaling artificial intelligence (AI) and high‑performance computing (HPC) markets. We’re proud to partner with imec on this milestone, marked by moments from the send-off to the system’s arrival. Together with imec, we’re accelerating High NA EUV extendibility for the next generations of advanced memory and compute. 🚀