zeroRISC

Excited to see zeroRISC, a Stata Capital portfolio company, pushing forward on post-quantum cryptography at the hardware level. As quantum computing advances, the security assumptions underpinning today’s digital infrastructure will need to evolve. Embedding quantum-resistant cryptography directly into silicon Root-of-Trust architectures will be critical for securing everything from cloud infrastructure to embedded and defense systems. Great to see the zeroRISC team building foundational security for the next generation of computing. #PostQuantum #Cybersecurity #Semiconductors #HardwareSecurity #DeepTech

GlobalPlatform at embedded world Exhibition&Conference this week! 10 March - Ilia Stolov - Designing EU CRA-compliant solutions with SESIP-Certified Devices 11 March - Gil Bernabeu - How eSIM is evolving into a Multi-Application Secure Platform 12 March - Dominic Rizzo - Open-Source Silicon: Driving Innovation, Trust, and Security in Embedded Systems

Production-ready lattice cryptography acceleration is here — and it's open source. Today we're sharing the story of how a multi-year collaboration between ZeroRISC engineers and academic researchers at Max Planck Institute for Security and Privacy (MPI-SP), Academia Sinica, Rivos Inc. and independents turned cutting-edge post-quantum cryptography research into production silicon and software. Our latest blog post details the full journey of integrating ML-KEM and ML-DSA acceleration into our open-source Asymmetric Cryptographic Co-processor (ACC). The results speak for themselves: 🔹8–10x latency improvement from baseline for ML-KEM and ML-DSA operations  🔹Memory-optimized ML-DSA signing fits in 32KiB — with slowdowns of just 82–138% vs. the 200–400% we originally anticipated  🔹52% speedup for ML-DSA operations through novel vectorized rejection sampling  🔹20% reduction in ML-KEM decapsulation cycles via a fully branchless sampling loop  🔹36–75% improvement in maximum frequency thanks to incorporating improved multiplier & adder designs and instruction set refinements by Ruben Niederhagen (Academia Sinica and University of Southern Denmark) and Hoang Nguyen Hien PHAM (MPI-SP) — with near-zero area cost This work is a testament to what happens when open-source development and academic research reinforce each other. Our research collaborators built innovative ISA extensions natively on our codebase. Our engineers then refined those artifacts — optimizing memory usage, improving the KMAC/ACC hardware interface, and driving design verification coverage — all within a shared repository that kept both sides in sync. The result: state-of-the-art post-quantum cryptography integrated into a production open-source silicon platform, ready for real-world deployment. We'll be presenting the full story of this collaboration at Real World Crypto 2026 (https://lnkd.in/etfVz7YV) in Taipei next month. Come find us there — we'd love to talk about what's next for PQC on Open Silicon. 📖 Read the full technical deep-dive: https://lnkd.in/ewcp-FvU 🔗 Explore the code: https://lnkd.in/emrDiqJt #PostQuantumCryptography #OpenSource #SiliconSecurity #MLKEM #MLDSA #RealWorldCrypto #PQC #zeroRISC

Fast. Flexible. Future-proof. Pick three. Two weeks ago, we shared a deep dive into how we sped up our embedded RSA implementation’s core operations by ~3x. This week, we’re sharing an aerial view of our cryptographic library, detailing how we maintain a cryptographic library that can support a root of trust in everything from the smallest IoT device to the largest server. Expect formal verification, static analysis, modular design–and of course, more performance tricks. Take a look at this week’s blog post, and see how we go from algorithms down to the metal in a way that meets performance and resource requirements while making life easy for developers and integrators. https://lnkd.in/gi9HhhHw #ZeroRISC #RSA #Cryptography #Security #Performance #Tech

Last week, we shared the mathematical trick behind our up-to-3.43x RSA speedup. This week, we’re diving head-first into how it works in raw assembly! To recap, the zeroRISC team integrated Chinese Remainder Theorem (CRT) modular exponentiation into our embedded RSA implementation, achieving ~3x speedups on core RSA operations. In this second of two blog posts, we explore the practical details of how this mathematical technique is actually implemented, addressing real-world goals like maintainability and certifiability under practical constraints, such as limited memory and extreme register pressure. See the full post below for a deep-dive on the practical engineering behind a large optimization like this, as well as the techniques, tooling, and tradeoffs we used to make it happen! https://lnkd.in/eQ6Ha4ry (If you missed it, see comments for part 1 on the theory behind the technique) #ZeroRISC #RSA #Cryptography #Security #Performance #Tech

We're excited to announce a major speedup for core RSA operations! Our team at zeroRISC has integrated Chinese Remainder Theorem (CRT) modular exponentiation into our embedded RSA implementation, resulting in a performance increase of up to 3.43x. This technique, though ancient in origin, is key to modern, high-performance cryptography. In this first of two blog posts, we dive into the mathematical basis for this change, explaining how a "divide and conquer" approach of working modulo each prime factor leads to massive efficiency gains. Read the full post here for the details behind this powerful technique, as well as real-life performance numbers -- and stay tuned for Part 2, where we'll share how we implemented it in practice! https://lnkd.in/ed8MhcwR #ZeroRISC #RSA #Cryptography #Security #Performance #Tech

ZeroRISC recently partnered with Rivos Inc. to implement FIPS 140-3 compliant OTP memory zeroization, ensuring cryptographic secrets are safely erased at end of life. This work highlights the importance of considering certification early and implementing it correctly – post-tapeout do-overs erode budgets and ruin weekends to fix. This illustrates the importance of considering certification early in silicon design, especially for security, and the care necessary to meet those requirements. You can learn more about how we’re aligning open silicon implementations with industry security standards for the long term in GlobalPlatform’s Trusted Open Silicon Task Force here: https://lnkd.in/dammQaHy #OpenSilicon #HardwareSecurity #FIPS1403 #TrustedHardware #ZeroRISC

Major congratulations to Rivos Inc. and its entire team for the successful, secure provisioning of its multi-chiplet SoC. We at zeroRISC are proud to have contributed to this milestone by providing secure provisioning appliances and cloud identity management from our Scale product line, guaranteeing deep integrity at manufacturing. Starting the certificate chain of trust during production enables complete supply chain protection, ensuring Root-of-Trust authentication and attestation of the lowest levels of code within the chip. This achievement highlights how composable, open platforms built for real manufacturing environments can accelerate secure system development while maintaining robust lifetime protection. Kudos to our partners at Rivos on their accomplishment! #RoT #OpenSilicon #ZeroRISC #SupplyChainIntegrity #SupplyChainSecurity

Check out our CEO and founder Dominic Rizzo’s recent GlobalPlatform TechTalk on open source for secure silicon. The talk covered: 💡 What open silicon is and how to apply the proven best practices from years of sustainable open source software projects to it 🛠️ How it addresses real-world challenges and delivers commercial value, as shown by the recently chartered GlobalPlatform task force on Trusted Open Silicon https://lnkd.in/eY62EJ6s 🔑 Key features of sustainable open source projects, especially in balancing community and commercial interests Watch the full talk here ▶️: https://lnkd.in/e2hh42uM

This summer, our MIT intern Yeabsira Hawaz dove into a critical challenge in open source silicon integration: enabling AXI compatibility while preserving TL-UL interconnect. ⚡ By designing a TL-UL to AXI bridge and an AXI AdapterReg, Yeabsira enabled open source IP to talk to commercial IP blocks and peripheral CSR interfaces 🖥️. This work ensures functional equivalence, supports incremental migration to AXI-native IP, and passes full-chip DV regression. Beyond RTL design, Yeabsira spent extensive time testing, debugging, and iterating - learning to integrate new modules into a large system while navigating real-world edge cases 🔧. The result? Open source silicon can now integrate more seamlessly with AXI-based systems, paving the way for smoother future adoption and verification. This internship is a perfect example of how hands-on work with real-world hardware challenges accelerates both innovation and engineering growth. Read the full blog here: https://lnkd.in/eBRzKWMf