/*******************************************************************************
 * File Name: cycfg_pins.h
 *
 * Description:
 * Pin configuration
 * This file was automatically generated and should not be modified.
 * Configurator Backend 3.60.0
 * device-db 4.34.0.9502
 * mtb-dsl-pse8xxgp 1.2.0.895
 *
 *******************************************************************************
 * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 ******************************************************************************/

#if !defined(CYCFG_PINS_H)
#define CYCFG_PINS_H

#include "cycfg_notices.h"
#include "cy_gpio.h"
#include "cycfg_routing.h"

#if defined(__cplusplus)
extern "C" {
#endif /* defined(__cplusplus) */

#define CYBSP_OSPI_RAM_CS_ENABLED 1U
#define CYBSP_OSPI_RAM_SS_ENABLED CYBSP_OSPI_RAM_CS_ENABLED
#define CYBSP_OSPI_RAM_CS_PORT GPIO_PRT0
#define CYBSP_OSPI_RAM_SS_PORT CYBSP_OSPI_RAM_CS_PORT
#define CYBSP_OSPI_RAM_CS_PORT_NUM 0U
#define CYBSP_OSPI_RAM_SS_PORT_NUM CYBSP_OSPI_RAM_CS_PORT_NUM
#define CYBSP_OSPI_RAM_CS_PIN 1U
#define CYBSP_OSPI_RAM_SS_PIN CYBSP_OSPI_RAM_CS_PIN
#define CYBSP_OSPI_RAM_CS_NUM 1U
#define CYBSP_OSPI_RAM_SS_NUM CYBSP_OSPI_RAM_CS_NUM
#define CYBSP_OSPI_RAM_CS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_OSPI_RAM_SS_DRIVEMODE CYBSP_OSPI_RAM_CS_DRIVEMODE
#define CYBSP_OSPI_RAM_CS_INIT_DRIVESTATE 1
#define CYBSP_OSPI_RAM_SS_INIT_DRIVESTATE CYBSP_OSPI_RAM_CS_INIT_DRIVESTATE
#ifndef ioss_0_port_0_pin_1_HSIOM
    #define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_OSPI_RAM_CS_HSIOM ioss_0_port_0_pin_1_HSIOM
#define CYBSP_OSPI_RAM_SS_HSIOM CYBSP_OSPI_RAM_CS_HSIOM
#define CYBSP_OSPI_RAM_CS_IRQ ioss_interrupts_gpio_0_IRQn
#define CYBSP_OSPI_RAM_SS_IRQ CYBSP_OSPI_RAM_CS_IRQ
#define CYBSP_QSPI_D0_ENABLED 1U
#define CYBSP_QSPI_D0_PORT (GPIO_PRT_Type *)SMIF0_CORE_SMIF_GPIO_SMIF_PRT0
#define CYBSP_QSPI_D0_PORT_NUM 1U
#define CYBSP_QSPI_D0_PIN 0U
#define CYBSP_QSPI_D0_NUM 0U
#define CYBSP_QSPI_D0_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_QSPI_D0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_1_pin_0_HSIOM
    #define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_ACT_15
#endif
#define CYBSP_QSPI_D0_HSIOM ioss_0_port_1_pin_0_HSIOM
#define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_1_IRQn
#define CYBSP_QSPI_D1_ENABLED 1U
#define CYBSP_QSPI_D1_PORT (GPIO_PRT_Type *)SMIF0_CORE_SMIF_GPIO_SMIF_PRT0
#define CYBSP_QSPI_D1_PORT_NUM 1U
#define CYBSP_QSPI_D1_PIN 1U
#define CYBSP_QSPI_D1_NUM 1U
#define CYBSP_QSPI_D1_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_QSPI_D1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_1_pin_1_HSIOM
    #define ioss_0_port_1_pin_1_HSIOM HSIOM_SEL_ACT_15
#endif
#define CYBSP_QSPI_D1_HSIOM ioss_0_port_1_pin_1_HSIOM
#define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_1_IRQn
#define CYBSP_QSPI_D2_ENABLED 1U
#define CYBSP_QSPI_D2_PORT (GPIO_PRT_Type *)SMIF0_CORE_SMIF_GPIO_SMIF_PRT0
#define CYBSP_QSPI_D2_PORT_NUM 1U
#define CYBSP_QSPI_D2_PIN 2U
#define CYBSP_QSPI_D2_NUM 2U
#define CYBSP_QSPI_D2_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_QSPI_D2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_1_pin_2_HSIOM
    #define ioss_0_port_1_pin_2_HSIOM HSIOM_SEL_ACT_15
#endif
#define CYBSP_QSPI_D2_HSIOM ioss_0_port_1_pin_2_HSIOM
#define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_1_IRQn
#define CYBSP_QSPI_D3_ENABLED 1U
#define CYBSP_QSPI_D3_PORT (GPIO_PRT_Type *)SMIF0_CORE_SMIF_GPIO_SMIF_PRT0
#define CYBSP_QSPI_D3_PORT_NUM 1U
#define CYBSP_QSPI_D3_PIN 3U
#define CYBSP_QSPI_D3_NUM 3U
#define CYBSP_QSPI_D3_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_QSPI_D3_INIT_DRIVESTATE 1
#ifndef ioss_0_port_1_pin_3_HSIOM
    #define ioss_0_port_1_pin_3_HSIOM HSIOM_SEL_ACT_15
#endif
#define CYBSP_QSPI_D3_HSIOM ioss_0_port_1_pin_3_HSIOM
#define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_1_IRQn
#define CYBSP_QSPI_CS_ENABLED 1U
#define CYBSP_QSPI_SS_ENABLED CYBSP_QSPI_CS_ENABLED
#define CYBSP_QSPI_CS_PORT GPIO_PRT2
#define CYBSP_QSPI_SS_PORT CYBSP_QSPI_CS_PORT
#define CYBSP_QSPI_CS_PORT_NUM 2U
#define CYBSP_QSPI_SS_PORT_NUM CYBSP_QSPI_CS_PORT_NUM
#define CYBSP_QSPI_CS_PIN 0U
#define CYBSP_QSPI_SS_PIN CYBSP_QSPI_CS_PIN
#define CYBSP_QSPI_CS_NUM 0U
#define CYBSP_QSPI_SS_NUM CYBSP_QSPI_CS_NUM
#define CYBSP_QSPI_CS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_QSPI_SS_DRIVEMODE CYBSP_QSPI_CS_DRIVEMODE
#define CYBSP_QSPI_CS_INIT_DRIVESTATE 1
#define CYBSP_QSPI_SS_INIT_DRIVESTATE CYBSP_QSPI_CS_INIT_DRIVESTATE
#ifndef ioss_0_port_2_pin_0_HSIOM
    #define ioss_0_port_2_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_QSPI_CS_HSIOM ioss_0_port_2_pin_0_HSIOM
#define CYBSP_QSPI_SS_HSIOM CYBSP_QSPI_CS_HSIOM
#define CYBSP_QSPI_CS_IRQ ioss_interrupts_gpio_2_IRQn
#define CYBSP_QSPI_SS_IRQ CYBSP_QSPI_CS_IRQ
#define CYBSP_I3C_SCL_ENABLED 1U
#define CYBSP_I3C_SCL_PORT GPIO_PRT3
#define CYBSP_I3C_SCL_PORT_NUM 3U
#define CYBSP_I3C_SCL_PIN 0U
#define CYBSP_I3C_SCL_NUM 0U
#define CYBSP_I3C_SCL_DRIVEMODE CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ
#define CYBSP_I3C_SCL_INIT_DRIVESTATE 1
#ifndef ioss_0_port_3_pin_0_HSIOM
    #define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_I3C_SCL_HSIOM ioss_0_port_3_pin_0_HSIOM
#define CYBSP_I3C_SCL_IRQ ioss_interrupts_gpio_3_IRQn
#define CYBSP_I3C_SDA_ENABLED 1U
#define CYBSP_I3C_SDA_PORT GPIO_PRT3
#define CYBSP_I3C_SDA_PORT_NUM 3U
#define CYBSP_I3C_SDA_PIN 1U
#define CYBSP_I3C_SDA_NUM 1U
#define CYBSP_I3C_SDA_DRIVEMODE CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ
#define CYBSP_I3C_SDA_INIT_DRIVESTATE 1
#ifndef ioss_0_port_3_pin_1_HSIOM
    #define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_I3C_SDA_HSIOM ioss_0_port_3_pin_1_HSIOM
#define CYBSP_I3C_SDA_IRQ ioss_interrupts_gpio_3_IRQn
#define CYBSP_OSPI_RAM_D0_ENABLED 1U
#define CYBSP_OSPI_RAM_D0_PORT (GPIO_PRT_Type *)SMIF1_CORE_SMIF_GPIO_SMIF_PRT0
#define CYBSP_OSPI_RAM_D0_PORT_NUM 4U
#define CYBSP_OSPI_RAM_D0_PIN 0U
#define CYBSP_OSPI_RAM_D0_NUM 0U
#define CYBSP_OSPI_RAM_D0_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_OSPI_RAM_D0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_4_pin_0_HSIOM
    #define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_ACT_15
#endif
#define CYBSP_OSPI_RAM_D0_HSIOM ioss_0_port_4_pin_0_HSIOM
#define CYBSP_OSPI_RAM_D0_IRQ ioss_interrupts_gpio_4_IRQn
#define CYBSP_OSPI_RAM_D1_ENABLED 1U
#define CYBSP_OSPI_RAM_D1_PORT (GPIO_PRT_Type *)SMIF1_CORE_SMIF_GPIO_SMIF_PRT0
#define CYBSP_OSPI_RAM_D1_PORT_NUM 4U
#define CYBSP_OSPI_RAM_D1_PIN 1U
#define CYBSP_OSPI_RAM_D1_NUM 1U
#define CYBSP_OSPI_RAM_D1_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_OSPI_RAM_D1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_4_pin_1_HSIOM
    #define ioss_0_port_4_pin_1_HSIOM HSIOM_SEL_ACT_15
#endif
#define CYBSP_OSPI_RAM_D1_HSIOM ioss_0_port_4_pin_1_HSIOM
#define CYBSP_OSPI_RAM_D1_IRQ ioss_interrupts_gpio_4_IRQn
#define CYBSP_OSPI_RAM_D2_ENABLED 1U
#define CYBSP_OSPI_RAM_D2_PORT (GPIO_PRT_Type *)SMIF1_CORE_SMIF_GPIO_SMIF_PRT0
#define CYBSP_OSPI_RAM_D2_PORT_NUM 4U
#define CYBSP_OSPI_RAM_D2_PIN 2U
#define CYBSP_OSPI_RAM_D2_NUM 2U
#define CYBSP_OSPI_RAM_D2_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_OSPI_RAM_D2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_4_pin_2_HSIOM
    #define ioss_0_port_4_pin_2_HSIOM HSIOM_SEL_ACT_15
#endif
#define CYBSP_OSPI_RAM_D2_HSIOM ioss_0_port_4_pin_2_HSIOM
#define CYBSP_OSPI_RAM_D2_IRQ ioss_interrupts_gpio_4_IRQn
#define CYBSP_OSPI_RAM_D3_ENABLED 1U
#define CYBSP_OSPI_RAM_D3_PORT (GPIO_PRT_Type *)SMIF1_CORE_SMIF_GPIO_SMIF_PRT0
#define CYBSP_OSPI_RAM_D3_PORT_NUM 4U
#define CYBSP_OSPI_RAM_D3_PIN 3U
#define CYBSP_OSPI_RAM_D3_NUM 3U
#define CYBSP_OSPI_RAM_D3_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_OSPI_RAM_D3_INIT_DRIVESTATE 1
#ifndef ioss_0_port_4_pin_3_HSIOM
    #define ioss_0_port_4_pin_3_HSIOM HSIOM_SEL_ACT_15
#endif
#define CYBSP_OSPI_RAM_D3_HSIOM ioss_0_port_4_pin_3_HSIOM
#define CYBSP_OSPI_RAM_D3_IRQ ioss_interrupts_gpio_4_IRQn
#define CYBSP_OSPI_RAM_D4_ENABLED 1U
#define CYBSP_OSPI_RAM_D4_PORT (GPIO_PRT_Type *)SMIF1_CORE_SMIF_GPIO_SMIF_PRT0
#define CYBSP_OSPI_RAM_D4_PORT_NUM 4U
#define CYBSP_OSPI_RAM_D4_PIN 4U
#define CYBSP_OSPI_RAM_D4_NUM 4U
#define CYBSP_OSPI_RAM_D4_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_OSPI_RAM_D4_INIT_DRIVESTATE 1
#ifndef ioss_0_port_4_pin_4_HSIOM
    #define ioss_0_port_4_pin_4_HSIOM HSIOM_SEL_ACT_15
#endif
#define CYBSP_OSPI_RAM_D4_HSIOM ioss_0_port_4_pin_4_HSIOM
#define CYBSP_OSPI_RAM_D4_IRQ ioss_interrupts_gpio_4_IRQn
#define CYBSP_OSPI_RAM_D5_ENABLED 1U
#define CYBSP_OSPI_RAM_D5_PORT (GPIO_PRT_Type *)SMIF1_CORE_SMIF_GPIO_SMIF_PRT0
#define CYBSP_OSPI_RAM_D5_PORT_NUM 4U
#define CYBSP_OSPI_RAM_D5_PIN 5U
#define CYBSP_OSPI_RAM_D5_NUM 5U
#define CYBSP_OSPI_RAM_D5_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_OSPI_RAM_D5_INIT_DRIVESTATE 1
#ifndef ioss_0_port_4_pin_5_HSIOM
    #define ioss_0_port_4_pin_5_HSIOM HSIOM_SEL_ACT_15
#endif
#define CYBSP_OSPI_RAM_D5_HSIOM ioss_0_port_4_pin_5_HSIOM
#define CYBSP_OSPI_RAM_D5_IRQ ioss_interrupts_gpio_4_IRQn
#define CYBSP_OSPI_RAM_D6_ENABLED 1U
#define CYBSP_OSPI_RAM_D6_PORT (GPIO_PRT_Type *)SMIF1_CORE_SMIF_GPIO_SMIF_PRT0
#define CYBSP_OSPI_RAM_D6_PORT_NUM 4U
#define CYBSP_OSPI_RAM_D6_PIN 6U
#define CYBSP_OSPI_RAM_D6_NUM 6U
#define CYBSP_OSPI_RAM_D6_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_OSPI_RAM_D6_INIT_DRIVESTATE 1
#ifndef ioss_0_port_4_pin_6_HSIOM
    #define ioss_0_port_4_pin_6_HSIOM HSIOM_SEL_ACT_15
#endif
#define CYBSP_OSPI_RAM_D6_HSIOM ioss_0_port_4_pin_6_HSIOM
#define CYBSP_OSPI_RAM_D6_IRQ ioss_interrupts_gpio_4_IRQn
#define CYBSP_OSPI_RAM_D7_ENABLED 1U
#define CYBSP_OSPI_RAM_D7_PORT (GPIO_PRT_Type *)SMIF1_CORE_SMIF_GPIO_SMIF_PRT0
#define CYBSP_OSPI_RAM_D7_PORT_NUM 4U
#define CYBSP_OSPI_RAM_D7_PIN 7U
#define CYBSP_OSPI_RAM_D7_NUM 7U
#define CYBSP_OSPI_RAM_D7_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_OSPI_RAM_D7_INIT_DRIVESTATE 1
#ifndef ioss_0_port_4_pin_7_HSIOM
    #define ioss_0_port_4_pin_7_HSIOM HSIOM_SEL_ACT_15
#endif
#define CYBSP_OSPI_RAM_D7_HSIOM ioss_0_port_4_pin_7_HSIOM
#define CYBSP_OSPI_RAM_D7_IRQ ioss_interrupts_gpio_4_IRQn
#define CYBSP_DEBUG_UART_RX_ENABLED 1U
#define CYBSP_DEBUG_UART_RX_PORT GPIO_PRT6
#define CYBSP_DEBUG_UART_RX_PORT_NUM 6U
#define CYBSP_DEBUG_UART_RX_PIN 5U
#define CYBSP_DEBUG_UART_RX_NUM 5U
#define CYBSP_DEBUG_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
#define CYBSP_DEBUG_UART_RX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_5_HSIOM
    #define ioss_0_port_6_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_DEBUG_UART_RX_HSIOM ioss_0_port_6_pin_5_HSIOM
#define CYBSP_DEBUG_UART_RX_IRQ ioss_interrupts_gpio_6_IRQn
#define CYBSP_DEBUG_UART_TX_ENABLED 1U
#define CYBSP_DEBUG_UART_TX_PORT GPIO_PRT6
#define CYBSP_DEBUG_UART_TX_PORT_NUM 6U
#define CYBSP_DEBUG_UART_TX_PIN 7U
#define CYBSP_DEBUG_UART_TX_NUM 7U
#define CYBSP_DEBUG_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_DEBUG_UART_TX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_7_HSIOM
    #define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_DEBUG_UART_TX_HSIOM ioss_0_port_6_pin_7_HSIOM
#define CYBSP_DEBUG_UART_TX_IRQ ioss_interrupts_gpio_6_IRQn
#define CYBSP_SW1_ENABLED 1U
#define CYBSP_USER_BTN1_ENABLED CYBSP_SW1_ENABLED
#define CYBSP_USER_BTN_ENABLED CYBSP_SW1_ENABLED
#define CYBSP_SW1_PORT GPIO_PRT7
#define CYBSP_USER_BTN1_PORT CYBSP_SW1_PORT
#define CYBSP_USER_BTN_PORT CYBSP_SW1_PORT
#define CYBSP_SW1_PORT_NUM 7U
#define CYBSP_USER_BTN1_PORT_NUM CYBSP_SW1_PORT_NUM
#define CYBSP_USER_BTN_PORT_NUM CYBSP_SW1_PORT_NUM
#define CYBSP_SW1_PIN 0U
#define CYBSP_USER_BTN1_PIN CYBSP_SW1_PIN
#define CYBSP_USER_BTN_PIN CYBSP_SW1_PIN
#define CYBSP_SW1_NUM 0U
#define CYBSP_USER_BTN1_NUM CYBSP_SW1_NUM
#define CYBSP_USER_BTN_NUM CYBSP_SW1_NUM
#define CYBSP_SW1_DRIVEMODE CY_GPIO_DM_PULLUP
#define CYBSP_USER_BTN1_DRIVEMODE CYBSP_SW1_DRIVEMODE
#define CYBSP_USER_BTN_DRIVEMODE CYBSP_SW1_DRIVEMODE
#define CYBSP_SW1_INIT_DRIVESTATE 1
#define CYBSP_USER_BTN1_INIT_DRIVESTATE CYBSP_SW1_INIT_DRIVESTATE
#define CYBSP_USER_BTN_INIT_DRIVESTATE CYBSP_SW1_INIT_DRIVESTATE
#ifndef ioss_0_port_7_pin_0_HSIOM
    #define ioss_0_port_7_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_SW1_HSIOM ioss_0_port_7_pin_0_HSIOM
#define CYBSP_USER_BTN1_HSIOM CYBSP_SW1_HSIOM
#define CYBSP_USER_BTN_HSIOM CYBSP_SW1_HSIOM
#define CYBSP_SW1_IRQ ioss_interrupts_gpio_7_IRQn
#define CYBSP_USER_BTN1_IRQ CYBSP_SW1_IRQ
#define CYBSP_USER_BTN_IRQ CYBSP_SW1_IRQ
#define CYBSP_EXT_CLK_ENABLED 1U
#define CYBSP_EXT_CLK_PORT GPIO_PRT7
#define CYBSP_EXT_CLK_PORT_NUM 7U
#define CYBSP_EXT_CLK_PIN 4U
#define CYBSP_EXT_CLK_NUM 4U
#define CYBSP_EXT_CLK_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_EXT_CLK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_7_pin_4_HSIOM
    #define ioss_0_port_7_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_EXT_CLK_HSIOM ioss_0_port_7_pin_4_HSIOM
#define CYBSP_EXT_CLK_IRQ ioss_interrupts_gpio_7_IRQn
#define CYBSP_I2C_SCL_1V8_ENABLED 1U
#define CYBSP_I2C_SCL_ENABLED CYBSP_I2C_SCL_1V8_ENABLED
#define CYBSP_I2C_SCL_1V8_PORT GPIO_PRT8
#define CYBSP_I2C_SCL_PORT CYBSP_I2C_SCL_1V8_PORT
#define CYBSP_I2C_SCL_1V8_PORT_NUM 8U
#define CYBSP_I2C_SCL_PORT_NUM CYBSP_I2C_SCL_1V8_PORT_NUM
#define CYBSP_I2C_SCL_1V8_PIN 0U
#define CYBSP_I2C_SCL_PIN CYBSP_I2C_SCL_1V8_PIN
#define CYBSP_I2C_SCL_1V8_NUM 0U
#define CYBSP_I2C_SCL_NUM CYBSP_I2C_SCL_1V8_NUM
#define CYBSP_I2C_SCL_1V8_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
#define CYBSP_I2C_SCL_DRIVEMODE CYBSP_I2C_SCL_1V8_DRIVEMODE
#define CYBSP_I2C_SCL_1V8_INIT_DRIVESTATE 1
#define CYBSP_I2C_SCL_INIT_DRIVESTATE CYBSP_I2C_SCL_1V8_INIT_DRIVESTATE
#ifndef ioss_0_port_8_pin_0_HSIOM
    #define ioss_0_port_8_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_I2C_SCL_1V8_HSIOM ioss_0_port_8_pin_0_HSIOM
#define CYBSP_I2C_SCL_HSIOM CYBSP_I2C_SCL_1V8_HSIOM
#define CYBSP_I2C_SCL_1V8_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_I2C_SCL_IRQ CYBSP_I2C_SCL_1V8_IRQ
#define CYBSP_I2C_SDA_1V8_ENABLED 1U
#define CYBSP_I2C_SDA_ENABLED CYBSP_I2C_SDA_1V8_ENABLED
#define CYBSP_I2C_SDA_1V8_PORT GPIO_PRT8
#define CYBSP_I2C_SDA_PORT CYBSP_I2C_SDA_1V8_PORT
#define CYBSP_I2C_SDA_1V8_PORT_NUM 8U
#define CYBSP_I2C_SDA_PORT_NUM CYBSP_I2C_SDA_1V8_PORT_NUM
#define CYBSP_I2C_SDA_1V8_PIN 1U
#define CYBSP_I2C_SDA_PIN CYBSP_I2C_SDA_1V8_PIN
#define CYBSP_I2C_SDA_1V8_NUM 1U
#define CYBSP_I2C_SDA_NUM CYBSP_I2C_SDA_1V8_NUM
#define CYBSP_I2C_SDA_1V8_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
#define CYBSP_I2C_SDA_DRIVEMODE CYBSP_I2C_SDA_1V8_DRIVEMODE
#define CYBSP_I2C_SDA_1V8_INIT_DRIVESTATE 1
#define CYBSP_I2C_SDA_INIT_DRIVESTATE CYBSP_I2C_SDA_1V8_INIT_DRIVESTATE
#ifndef ioss_0_port_8_pin_1_HSIOM
    #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_I2C_SDA_1V8_HSIOM ioss_0_port_8_pin_1_HSIOM
#define CYBSP_I2C_SDA_HSIOM CYBSP_I2C_SDA_1V8_HSIOM
#define CYBSP_I2C_SDA_1V8_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_I2C_SDA_IRQ CYBSP_I2C_SDA_1V8_IRQ
#define CYBSP_PDM_CLK_ENABLED 1U
#define CYBSP_PDM_CLK_PORT GPIO_PRT8
#define CYBSP_PDM_CLK_PORT_NUM 8U
#define CYBSP_PDM_CLK_PIN 5U
#define CYBSP_PDM_CLK_NUM 5U
#define CYBSP_PDM_CLK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_PDM_CLK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_5_HSIOM
    #define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_PDM_CLK_HSIOM ioss_0_port_8_pin_5_HSIOM
#define CYBSP_PDM_CLK_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_PDM_DATA_ENABLED 1U
#define CYBSP_PDM_DATA_PORT GPIO_PRT8
#define CYBSP_PDM_DATA_PORT_NUM 8U
#define CYBSP_PDM_DATA_PIN 6U
#define CYBSP_PDM_DATA_NUM 6U
#define CYBSP_PDM_DATA_DRIVEMODE CY_GPIO_DM_HIGHZ
#define CYBSP_PDM_DATA_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_6_HSIOM
    #define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_PDM_DATA_HSIOM ioss_0_port_8_pin_6_HSIOM
#define CYBSP_PDM_DATA_IRQ ioss_interrupts_gpio_8_IRQn
#define CYBSP_SERIAL_INT_0_ENABLED 1U
#define CYBSP_SERIAL_INT_0_PORT GPIO_PRT9
#define CYBSP_SERIAL_INT_0_PORT_NUM 9U
#define CYBSP_SERIAL_INT_0_PIN 0U
#define CYBSP_SERIAL_INT_0_NUM 0U
#define CYBSP_SERIAL_INT_0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_SERIAL_INT_0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_9_pin_0_HSIOM
    #define ioss_0_port_9_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_SERIAL_INT_0_HSIOM ioss_0_port_9_pin_0_HSIOM
#define CYBSP_SERIAL_INT_0_IRQ ioss_interrupts_gpio_9_IRQn
#define CYBSP_SERIAL_INT_2_ENABLED 1U
#define CYBSP_SERIAL_INT_2_PORT GPIO_PRT9
#define CYBSP_SERIAL_INT_2_PORT_NUM 9U
#define CYBSP_SERIAL_INT_2_PIN 2U
#define CYBSP_SERIAL_INT_2_NUM 2U
#define CYBSP_SERIAL_INT_2_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_SERIAL_INT_2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_9_pin_2_HSIOM
    #define ioss_0_port_9_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_SERIAL_INT_2_HSIOM ioss_0_port_9_pin_2_HSIOM
#define CYBSP_SERIAL_INT_2_IRQ ioss_interrupts_gpio_9_IRQn
#define CYBSP_BT_UART_RX_ENABLED 1U
#define CYBSP_BT_UART_RX_PORT GPIO_PRT10
#define CYBSP_BT_UART_RX_PORT_NUM 10U
#define CYBSP_BT_UART_RX_PIN 0U
#define CYBSP_BT_UART_RX_NUM 0U
#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_10_pin_0_HSIOM
    #define ioss_0_port_10_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_10_pin_0_HSIOM
#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_10_IRQn
#define CYBSP_BT_UART_TX_ENABLED 1U
#define CYBSP_BT_UART_TX_PORT GPIO_PRT10
#define CYBSP_BT_UART_TX_PORT_NUM 10U
#define CYBSP_BT_UART_TX_PIN 1U
#define CYBSP_BT_UART_TX_NUM 1U
#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_10_pin_1_HSIOM
    #define ioss_0_port_10_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_10_pin_1_HSIOM
#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_10_IRQn
#define CYBSP_BT_UART_CTS_ENABLED 1U
#define CYBSP_BT_UART_CTS_PORT GPIO_PRT10
#define CYBSP_BT_UART_CTS_PORT_NUM 10U
#define CYBSP_BT_UART_CTS_PIN 2U
#define CYBSP_BT_UART_CTS_NUM 2U
#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 0
#ifndef ioss_0_port_10_pin_2_HSIOM
    #define ioss_0_port_10_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_10_pin_2_HSIOM
#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_10_IRQn
#define CYBSP_BT_UART_RTS_ENABLED 1U
#define CYBSP_BT_UART_RTS_PORT GPIO_PRT10
#define CYBSP_BT_UART_RTS_PORT_NUM 10U
#define CYBSP_BT_UART_RTS_PIN 3U
#define CYBSP_BT_UART_RTS_NUM 3U
#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 0
#ifndef ioss_0_port_10_pin_3_HSIOM
    #define ioss_0_port_10_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_10_pin_3_HSIOM
#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_10_IRQn
#define CYBSP_BT_HOST_WAKE_ENABLED 1U
#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT10
#define CYBSP_BT_HOST_WAKE_PORT_NUM 10U
#define CYBSP_BT_HOST_WAKE_PIN 4U
#define CYBSP_BT_HOST_WAKE_NUM 4U
#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_HIGHZ
#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0
#ifndef ioss_0_port_10_pin_4_HSIOM
    #define ioss_0_port_10_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_10_pin_4_HSIOM
#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_10_IRQn
#define CYBSP_USER_LED2_ENABLED 1U
#define CYBSP_USER_LED2_PORT GPIO_PRT10
#define CYBSP_USER_LED2_PORT_NUM 10U
#define CYBSP_USER_LED2_PIN 5U
#define CYBSP_USER_LED2_NUM 5U
#define CYBSP_USER_LED2_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_USER_LED2_INIT_DRIVESTATE 0
#ifndef ioss_0_port_10_pin_5_HSIOM
    #define ioss_0_port_10_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_USER_LED2_HSIOM ioss_0_port_10_pin_5_HSIOM
#define CYBSP_USER_LED2_IRQ ioss_interrupts_gpio_10_IRQn
#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U
#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT10
#define CYBSP_BT_DEVICE_WAKE_PORT_NUM 10U
#define CYBSP_BT_DEVICE_WAKE_PIN 6U
#define CYBSP_BT_DEVICE_WAKE_NUM 6U
#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0
#ifndef ioss_0_port_10_pin_6_HSIOM
    #define ioss_0_port_10_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_10_pin_6_HSIOM
#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_10_IRQn
#define CYBSP_USER_LED1_ENABLED 1U
#define CYBSP_USER_LED_ENABLED CYBSP_USER_LED1_ENABLED
#define CYBSP_USER_LED1_PORT GPIO_PRT10
#define CYBSP_USER_LED_PORT CYBSP_USER_LED1_PORT
#define CYBSP_USER_LED1_PORT_NUM 10U
#define CYBSP_USER_LED_PORT_NUM CYBSP_USER_LED1_PORT_NUM
#define CYBSP_USER_LED1_PIN 7U
#define CYBSP_USER_LED_PIN CYBSP_USER_LED1_PIN
#define CYBSP_USER_LED1_NUM 7U
#define CYBSP_USER_LED_NUM CYBSP_USER_LED1_NUM
#define CYBSP_USER_LED1_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_USER_LED_DRIVEMODE CYBSP_USER_LED1_DRIVEMODE
#define CYBSP_USER_LED1_INIT_DRIVESTATE 0
#define CYBSP_USER_LED_INIT_DRIVESTATE CYBSP_USER_LED1_INIT_DRIVESTATE
#ifndef ioss_0_port_10_pin_7_HSIOM
    #define ioss_0_port_10_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_USER_LED1_HSIOM ioss_0_port_10_pin_7_HSIOM
#define CYBSP_USER_LED_HSIOM CYBSP_USER_LED1_HSIOM
#define CYBSP_USER_LED1_IRQ ioss_interrupts_gpio_10_IRQn
#define CYBSP_USER_LED_IRQ CYBSP_USER_LED1_IRQ
#define CYBSP_BT_POWER_ENABLED 1U
#define CYBSP_BT_POWER_PORT GPIO_PRT11
#define CYBSP_BT_POWER_PORT_NUM 11U
#define CYBSP_BT_POWER_PIN 0U
#define CYBSP_BT_POWER_NUM 0U
#define CYBSP_BT_POWER_DRIVEMODE CY_GPIO_DM_PULLUP
#define CYBSP_BT_POWER_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_0_HSIOM
    #define ioss_0_port_11_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_BT_POWER_HSIOM ioss_0_port_11_pin_0_HSIOM
#define CYBSP_BT_POWER_IRQ ioss_interrupts_gpio_11_IRQn
#define CYBSP_DVP_CAM_PCLK_ENABLED 1U
#define CYBSP_DVP_CAM_PCLK_PORT GPIO_PRT11
#define CYBSP_DVP_CAM_PCLK_PORT_NUM 11U
#define CYBSP_DVP_CAM_PCLK_PIN 1U
#define CYBSP_DVP_CAM_PCLK_NUM 1U
#define CYBSP_DVP_CAM_PCLK_DRIVEMODE CY_GPIO_DM_HIGHZ
#define CYBSP_DVP_CAM_PCLK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_1_HSIOM
    #define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_DVP_CAM_PCLK_HSIOM ioss_0_port_11_pin_1_HSIOM
#define CYBSP_DVP_CAM_PCLK_IRQ ioss_interrupts_gpio_11_IRQn
#define CYBSP_WIFI_WL_REG_ON_ENABLED 1U
#define CYBSP_WIFI_WL_REG_ON_PORT GPIO_PRT11
#define CYBSP_WIFI_WL_REG_ON_PORT_NUM 11U
#define CYBSP_WIFI_WL_REG_ON_PIN 4U
#define CYBSP_WIFI_WL_REG_ON_NUM 4U
#define CYBSP_WIFI_WL_REG_ON_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
#define CYBSP_WIFI_WL_REG_ON_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_4_HSIOM
    #define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_WIFI_WL_REG_ON_HSIOM ioss_0_port_11_pin_4_HSIOM
#define CYBSP_WIFI_WL_REG_ON_IRQ ioss_interrupts_gpio_11_IRQn
#define CYBSP_WIFI_HOST_WAKE_ENABLED 1U
#define CYBSP_WIFI_HOST_WAKE_PORT GPIO_PRT11
#define CYBSP_WIFI_HOST_WAKE_PORT_NUM 11U
#define CYBSP_WIFI_HOST_WAKE_PIN 6U
#define CYBSP_WIFI_HOST_WAKE_NUM 6U
#define CYBSP_WIFI_HOST_WAKE_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
#define CYBSP_WIFI_HOST_WAKE_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_6_HSIOM
    #define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_WIFI_HOST_WAKE_HSIOM ioss_0_port_11_pin_6_HSIOM
#define CYBSP_WIFI_HOST_WAKE_IRQ ioss_interrupts_gpio_11_IRQn
#define CYBSP_WIFI_SDIO_CLK_ENABLED 1U
#define CYBSP_WIFI_SDIO_CLK_PORT GPIO_PRT12
#define CYBSP_WIFI_SDIO_CLK_PORT_NUM 12U
#define CYBSP_WIFI_SDIO_CLK_PIN 0U
#define CYBSP_WIFI_SDIO_CLK_NUM 0U
#define CYBSP_WIFI_SDIO_CLK_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_WIFI_SDIO_CLK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_12_pin_0_HSIOM
    #define ioss_0_port_12_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_WIFI_SDIO_CLK_HSIOM ioss_0_port_12_pin_0_HSIOM
#define CYBSP_WIFI_SDIO_CLK_IRQ ioss_interrupts_gpio_12_IRQn
#define CYBSP_WIFI_SDIO_D0_ENABLED 1U
#define CYBSP_WIFI_SDIO_D0_PORT GPIO_PRT12
#define CYBSP_WIFI_SDIO_D0_PORT_NUM 12U
#define CYBSP_WIFI_SDIO_D0_PIN 1U
#define CYBSP_WIFI_SDIO_D0_NUM 1U
#define CYBSP_WIFI_SDIO_D0_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_WIFI_SDIO_D0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_12_pin_1_HSIOM
    #define ioss_0_port_12_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_WIFI_SDIO_D0_HSIOM ioss_0_port_12_pin_1_HSIOM
#define CYBSP_WIFI_SDIO_D0_IRQ ioss_interrupts_gpio_12_IRQn
#define CYBSP_WIFI_SDIO_D1_ENABLED 1U
#define CYBSP_WIFI_SDIO_D1_PORT GPIO_PRT12
#define CYBSP_WIFI_SDIO_D1_PORT_NUM 12U
#define CYBSP_WIFI_SDIO_D1_PIN 2U
#define CYBSP_WIFI_SDIO_D1_NUM 2U
#define CYBSP_WIFI_SDIO_D1_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_WIFI_SDIO_D1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_12_pin_2_HSIOM
    #define ioss_0_port_12_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_WIFI_SDIO_D1_HSIOM ioss_0_port_12_pin_2_HSIOM
#define CYBSP_WIFI_SDIO_D1_IRQ ioss_interrupts_gpio_12_IRQn
#define CYBSP_I2S_TX_FSYNC_ENABLED 1U
#define CYBSP_I2S_TX_FSYNC_PORT GPIO_PRT12
#define CYBSP_I2S_TX_FSYNC_PORT_NUM 12U
#define CYBSP_I2S_TX_FSYNC_PIN 3U
#define CYBSP_I2S_TX_FSYNC_NUM 3U
#define CYBSP_I2S_TX_FSYNC_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_I2S_TX_FSYNC_INIT_DRIVESTATE 1
#ifndef ioss_0_port_12_pin_3_HSIOM
    #define ioss_0_port_12_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_I2S_TX_FSYNC_HSIOM ioss_0_port_12_pin_3_HSIOM
#define CYBSP_I2S_TX_FSYNC_IRQ ioss_interrupts_gpio_12_IRQn
#define CYBSP_WIFI_SDIO_D2_ENABLED 1U
#define CYBSP_WIFI_SDIO_D2_PORT GPIO_PRT12
#define CYBSP_WIFI_SDIO_D2_PORT_NUM 12U
#define CYBSP_WIFI_SDIO_D2_PIN 4U
#define CYBSP_WIFI_SDIO_D2_NUM 4U
#define CYBSP_WIFI_SDIO_D2_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_WIFI_SDIO_D2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_12_pin_4_HSIOM
    #define ioss_0_port_12_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_WIFI_SDIO_D2_HSIOM ioss_0_port_12_pin_4_HSIOM
#define CYBSP_WIFI_SDIO_D2_IRQ ioss_interrupts_gpio_12_IRQn
#define CYBSP_WIFI_SDIO_D3_ENABLED 1U
#define CYBSP_WIFI_SDIO_D3_PORT GPIO_PRT12
#define CYBSP_WIFI_SDIO_D3_PORT_NUM 12U
#define CYBSP_WIFI_SDIO_D3_PIN 5U
#define CYBSP_WIFI_SDIO_D3_NUM 5U
#define CYBSP_WIFI_SDIO_D3_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_WIFI_SDIO_D3_INIT_DRIVESTATE 1
#ifndef ioss_0_port_12_pin_5_HSIOM
    #define ioss_0_port_12_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_WIFI_SDIO_D3_HSIOM ioss_0_port_12_pin_5_HSIOM
#define CYBSP_WIFI_SDIO_D3_IRQ ioss_interrupts_gpio_12_IRQn
#define CYBSP_DVP_CAM_D0_ENABLED 1U
#define CYBSP_DVP_CAM_D0_PORT GPIO_PRT16
#define CYBSP_DVP_CAM_D0_PORT_NUM 16U
#define CYBSP_DVP_CAM_D0_PIN 0U
#define CYBSP_DVP_CAM_D0_NUM 0U
#define CYBSP_DVP_CAM_D0_DRIVEMODE CY_GPIO_DM_HIGHZ
#define CYBSP_DVP_CAM_D0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_16_pin_0_HSIOM
    #define ioss_0_port_16_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_DVP_CAM_D0_HSIOM ioss_0_port_16_pin_0_HSIOM
#define CYBSP_DVP_CAM_D0_IRQ ioss_interrupts_gpio_16_IRQn
#define CYBSP_DVP_CAM_D1_ENABLED 1U
#define CYBSP_DVP_CAM_D1_PORT GPIO_PRT16
#define CYBSP_DVP_CAM_D1_PORT_NUM 16U
#define CYBSP_DVP_CAM_D1_PIN 1U
#define CYBSP_DVP_CAM_D1_NUM 1U
#define CYBSP_DVP_CAM_D1_DRIVEMODE CY_GPIO_DM_HIGHZ
#define CYBSP_DVP_CAM_D1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_16_pin_1_HSIOM
    #define ioss_0_port_16_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_DVP_CAM_D1_HSIOM ioss_0_port_16_pin_1_HSIOM
#define CYBSP_DVP_CAM_D1_IRQ ioss_interrupts_gpio_16_IRQn
#define CYBSP_DVP_CAM_D2_ENABLED 1U
#define CYBSP_DVP_CAM_D2_PORT GPIO_PRT16
#define CYBSP_DVP_CAM_D2_PORT_NUM 16U
#define CYBSP_DVP_CAM_D2_PIN 2U
#define CYBSP_DVP_CAM_D2_NUM 2U
#define CYBSP_DVP_CAM_D2_DRIVEMODE CY_GPIO_DM_HIGHZ
#define CYBSP_DVP_CAM_D2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_16_pin_2_HSIOM
    #define ioss_0_port_16_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_DVP_CAM_D2_HSIOM ioss_0_port_16_pin_2_HSIOM
#define CYBSP_DVP_CAM_D2_IRQ ioss_interrupts_gpio_16_IRQn
#define CYBSP_DVP_CAM_D3_ENABLED 1U
#define CYBSP_DVP_CAM_D3_PORT GPIO_PRT16
#define CYBSP_DVP_CAM_D3_PORT_NUM 16U
#define CYBSP_DVP_CAM_D3_PIN 3U
#define CYBSP_DVP_CAM_D3_NUM 3U
#define CYBSP_DVP_CAM_D3_DRIVEMODE CY_GPIO_DM_HIGHZ
#define CYBSP_DVP_CAM_D3_INIT_DRIVESTATE 1
#ifndef ioss_0_port_16_pin_3_HSIOM
    #define ioss_0_port_16_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_DVP_CAM_D3_HSIOM ioss_0_port_16_pin_3_HSIOM
#define CYBSP_DVP_CAM_D3_IRQ ioss_interrupts_gpio_16_IRQn
#define CYBSP_DVP_CAM_D4_ENABLED 1U
#define CYBSP_DVP_CAM_D4_PORT GPIO_PRT16
#define CYBSP_DVP_CAM_D4_PORT_NUM 16U
#define CYBSP_DVP_CAM_D4_PIN 4U
#define CYBSP_DVP_CAM_D4_NUM 4U
#define CYBSP_DVP_CAM_D4_DRIVEMODE CY_GPIO_DM_HIGHZ
#define CYBSP_DVP_CAM_D4_INIT_DRIVESTATE 1
#ifndef ioss_0_port_16_pin_4_HSIOM
    #define ioss_0_port_16_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_DVP_CAM_D4_HSIOM ioss_0_port_16_pin_4_HSIOM
#define CYBSP_DVP_CAM_D4_IRQ ioss_interrupts_gpio_16_IRQn
#define CYBSP_DVP_CAM_D5_ENABLED 1U
#define CYBSP_DVP_CAM_D5_PORT GPIO_PRT16
#define CYBSP_DVP_CAM_D5_PORT_NUM 16U
#define CYBSP_DVP_CAM_D5_PIN 5U
#define CYBSP_DVP_CAM_D5_NUM 5U
#define CYBSP_DVP_CAM_D5_DRIVEMODE CY_GPIO_DM_HIGHZ
#define CYBSP_DVP_CAM_D5_INIT_DRIVESTATE 1
#ifndef ioss_0_port_16_pin_5_HSIOM
    #define ioss_0_port_16_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_DVP_CAM_D5_HSIOM ioss_0_port_16_pin_5_HSIOM
#define CYBSP_DVP_CAM_D5_IRQ ioss_interrupts_gpio_16_IRQn
#define CYBSP_DVP_CAM_D6_ENABLED 1U
#define CYBSP_DVP_CAM_D6_PORT GPIO_PRT16
#define CYBSP_DVP_CAM_D6_PORT_NUM 16U
#define CYBSP_DVP_CAM_D6_PIN 6U
#define CYBSP_DVP_CAM_D6_NUM 6U
#define CYBSP_DVP_CAM_D6_DRIVEMODE CY_GPIO_DM_HIGHZ
#define CYBSP_DVP_CAM_D6_INIT_DRIVESTATE 1
#ifndef ioss_0_port_16_pin_6_HSIOM
    #define ioss_0_port_16_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_DVP_CAM_D6_HSIOM ioss_0_port_16_pin_6_HSIOM
#define CYBSP_DVP_CAM_D6_IRQ ioss_interrupts_gpio_16_IRQn
#define CYBSP_DVP_CAM_D7_ENABLED 1U
#define CYBSP_DVP_CAM_D7_PORT GPIO_PRT16
#define CYBSP_DVP_CAM_D7_PORT_NUM 16U
#define CYBSP_DVP_CAM_D7_PIN 7U
#define CYBSP_DVP_CAM_D7_NUM 7U
#define CYBSP_DVP_CAM_D7_DRIVEMODE CY_GPIO_DM_HIGHZ
#define CYBSP_DVP_CAM_D7_INIT_DRIVESTATE 1
#ifndef ioss_0_port_16_pin_7_HSIOM
    #define ioss_0_port_16_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_DVP_CAM_D7_HSIOM ioss_0_port_16_pin_7_HSIOM
#define CYBSP_DVP_CAM_D7_IRQ ioss_interrupts_gpio_16_IRQn
#define CYBSP_I2C_SCL_3V3_ENABLED 1U
#define CYBSP_I2C_SCL_3V3_PORT GPIO_PRT17
#define CYBSP_I2C_SCL_3V3_PORT_NUM 17U
#define CYBSP_I2C_SCL_3V3_PIN 0U
#define CYBSP_I2C_SCL_3V3_NUM 0U
#define CYBSP_I2C_SCL_3V3_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
#define CYBSP_I2C_SCL_3V3_INIT_DRIVESTATE 1
#ifndef ioss_0_port_17_pin_0_HSIOM
    #define ioss_0_port_17_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_I2C_SCL_3V3_HSIOM ioss_0_port_17_pin_0_HSIOM
#define CYBSP_I2C_SCL_3V3_IRQ ioss_interrupts_gpio_17_IRQn
#define CYBSP_I2C_SDA_3V3_ENABLED 1U
#define CYBSP_I2C_SDA_3V3_PORT GPIO_PRT17
#define CYBSP_I2C_SDA_3V3_PORT_NUM 17U
#define CYBSP_I2C_SDA_3V3_PIN 1U
#define CYBSP_I2C_SDA_3V3_NUM 1U
#define CYBSP_I2C_SDA_3V3_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
#define CYBSP_I2C_SDA_3V3_INIT_DRIVESTATE 1
#ifndef ioss_0_port_17_pin_1_HSIOM
    #define ioss_0_port_17_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_I2C_SDA_3V3_HSIOM ioss_0_port_17_pin_1_HSIOM
#define CYBSP_I2C_SDA_3V3_IRQ ioss_interrupts_gpio_17_IRQn
#define CYBSP_DVP_CAM_VSYNC_ENABLED 1U
#define CYBSP_DVP_CAM_VSYNC_PORT GPIO_PRT17
#define CYBSP_DVP_CAM_VSYNC_PORT_NUM 17U
#define CYBSP_DVP_CAM_VSYNC_PIN 2U
#define CYBSP_DVP_CAM_VSYNC_NUM 2U
#define CYBSP_DVP_CAM_VSYNC_DRIVEMODE CY_GPIO_DM_HIGHZ
#define CYBSP_DVP_CAM_VSYNC_INIT_DRIVESTATE 0
#ifndef ioss_0_port_17_pin_2_HSIOM
    #define ioss_0_port_17_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_DVP_CAM_VSYNC_HSIOM ioss_0_port_17_pin_2_HSIOM
#define CYBSP_DVP_CAM_VSYNC_IRQ ioss_interrupts_gpio_17_IRQn
#define CYBSP_DVP_CAM_HREF_ENABLED 1U
#define CYBSP_DVP_CAM_HREF_PORT GPIO_PRT17
#define CYBSP_DVP_CAM_HREF_PORT_NUM 17U
#define CYBSP_DVP_CAM_HREF_PIN 3U
#define CYBSP_DVP_CAM_HREF_NUM 3U
#define CYBSP_DVP_CAM_HREF_DRIVEMODE CY_GPIO_DM_HIGHZ
#define CYBSP_DVP_CAM_HREF_INIT_DRIVESTATE 1
#ifndef ioss_0_port_17_pin_3_HSIOM
    #define ioss_0_port_17_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_DVP_CAM_HREF_HSIOM ioss_0_port_17_pin_3_HSIOM
#define CYBSP_DVP_CAM_HREF_IRQ ioss_interrupts_gpio_17_IRQn
#define CYBSP_DVP_CAM_XCLK_ENABLED 1U
#define CYBSP_DVP_CAM_XCLK_PORT GPIO_PRT17
#define CYBSP_DVP_CAM_XCLK_PORT_NUM 17U
#define CYBSP_DVP_CAM_XCLK_PIN 4U
#define CYBSP_DVP_CAM_XCLK_NUM 4U
#define CYBSP_DVP_CAM_XCLK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_DVP_CAM_XCLK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_17_pin_4_HSIOM
    #define ioss_0_port_17_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_DVP_CAM_XCLK_HSIOM ioss_0_port_17_pin_4_HSIOM
#define CYBSP_DVP_CAM_XCLK_IRQ ioss_interrupts_gpio_17_IRQn
#define CYBSP_DVP_CAM_RESET_ENABLED 1U
#define CYBSP_DVP_CAM_RESET_PORT GPIO_PRT17
#define CYBSP_DVP_CAM_RESET_PORT_NUM 17U
#define CYBSP_DVP_CAM_RESET_PIN 5U
#define CYBSP_DVP_CAM_RESET_NUM 5U
#define CYBSP_DVP_CAM_RESET_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_DVP_CAM_RESET_INIT_DRIVESTATE 1
#ifndef ioss_0_port_17_pin_5_HSIOM
    #define ioss_0_port_17_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_DVP_CAM_RESET_HSIOM ioss_0_port_17_pin_5_HSIOM
#define CYBSP_DVP_CAM_RESET_IRQ ioss_interrupts_gpio_17_IRQn
#define CYBSP_DVP_CAM_PWDN_ENABLED 1U
#define CYBSP_DVP_CAM_PWDN_PORT GPIO_PRT17
#define CYBSP_DVP_CAM_PWDN_PORT_NUM 17U
#define CYBSP_DVP_CAM_PWDN_PIN 7U
#define CYBSP_DVP_CAM_PWDN_NUM 7U
#define CYBSP_DVP_CAM_PWDN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_DVP_CAM_PWDN_INIT_DRIVESTATE 0
#ifndef ioss_0_port_17_pin_7_HSIOM
    #define ioss_0_port_17_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_DVP_CAM_PWDN_HSIOM ioss_0_port_17_pin_7_HSIOM
#define CYBSP_DVP_CAM_PWDN_IRQ ioss_interrupts_gpio_17_IRQn
#define CYBSP_WCO_OUT_ENABLED 1U
#define CYBSP_WCO_OUT_PORT GPIO_PRT18
#define CYBSP_WCO_OUT_PORT_NUM 18U
#define CYBSP_WCO_OUT_PIN 0U
#define CYBSP_WCO_OUT_NUM 0U
#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
#ifndef ioss_0_port_18_pin_0_HSIOM
    #define ioss_0_port_18_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_WCO_OUT_HSIOM ioss_0_port_18_pin_0_HSIOM
#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_18_IRQn
#define CYBSP_WCO_IN_ENABLED 1U
#define CYBSP_WCO_IN_PORT GPIO_PRT18
#define CYBSP_WCO_IN_PORT_NUM 18U
#define CYBSP_WCO_IN_PIN 1U
#define CYBSP_WCO_IN_NUM 1U
#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
#ifndef ioss_0_port_18_pin_1_HSIOM
    #define ioss_0_port_18_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_WCO_IN_HSIOM ioss_0_port_18_pin_1_HSIOM
#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_18_IRQn
#define CYBSP_ECO_IN_ENABLED 1U
#define CYBSP_ECO_IN_PORT GPIO_PRT19
#define CYBSP_ECO_IN_PORT_NUM 19U
#define CYBSP_ECO_IN_PIN 0U
#define CYBSP_ECO_IN_NUM 0U
#define CYBSP_ECO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_ECO_IN_INIT_DRIVESTATE 1
#ifndef ioss_0_port_19_pin_0_HSIOM
    #define ioss_0_port_19_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_ECO_IN_HSIOM ioss_0_port_19_pin_0_HSIOM
#define CYBSP_ECO_IN_IRQ ioss_interrupts_gpio_19_IRQn
#define CYBSP_ECO_OUT_ENABLED 1U
#define CYBSP_ECO_OUT_PORT GPIO_PRT19
#define CYBSP_ECO_OUT_PORT_NUM 19U
#define CYBSP_ECO_OUT_PIN 1U
#define CYBSP_ECO_OUT_NUM 1U
#define CYBSP_ECO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_ECO_OUT_INIT_DRIVESTATE 1
#ifndef ioss_0_port_19_pin_1_HSIOM
    #define ioss_0_port_19_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_ECO_OUT_HSIOM ioss_0_port_19_pin_1_HSIOM
#define CYBSP_ECO_OUT_IRQ ioss_interrupts_gpio_19_IRQn
#define CYBSP_RADAR_INT_ENABLED 1U
#define CYBSP_RADAR_INT_PORT GPIO_PRT20
#define CYBSP_RADAR_INT_PORT_NUM 20U
#define CYBSP_RADAR_INT_PIN 3U
#define CYBSP_RADAR_INT_NUM 3U
#define CYBSP_RADAR_INT_DRIVEMODE CY_GPIO_DM_PULLDOWN_IN_OFF
#define CYBSP_RADAR_INT_INIT_DRIVESTATE 0
#ifndef ioss_0_port_20_pin_3_HSIOM
    #define ioss_0_port_20_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_RADAR_INT_HSIOM ioss_0_port_20_pin_3_HSIOM
#define CYBSP_RADAR_INT_IRQ ioss_interrupts_gpio_20_IRQn
#define CYBSP_LED_RGB_GREEN_ENABLED 1U
#define CYBSP_USER_LED5_ENABLED CYBSP_LED_RGB_GREEN_ENABLED
#define CYBSP_LED_RGB_GREEN_PORT GPIO_PRT20
#define CYBSP_USER_LED5_PORT CYBSP_LED_RGB_GREEN_PORT
#define CYBSP_LED_RGB_GREEN_PORT_NUM 20U
#define CYBSP_USER_LED5_PORT_NUM CYBSP_LED_RGB_GREEN_PORT_NUM
#define CYBSP_LED_RGB_GREEN_PIN 4U
#define CYBSP_USER_LED5_PIN CYBSP_LED_RGB_GREEN_PIN
#define CYBSP_LED_RGB_GREEN_NUM 4U
#define CYBSP_USER_LED5_NUM CYBSP_LED_RGB_GREEN_NUM
#define CYBSP_LED_RGB_GREEN_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_USER_LED5_DRIVEMODE CYBSP_LED_RGB_GREEN_DRIVEMODE
#define CYBSP_LED_RGB_GREEN_INIT_DRIVESTATE 0
#define CYBSP_USER_LED5_INIT_DRIVESTATE CYBSP_LED_RGB_GREEN_INIT_DRIVESTATE
#ifndef ioss_0_port_20_pin_4_HSIOM
    #define ioss_0_port_20_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_LED_RGB_GREEN_HSIOM ioss_0_port_20_pin_4_HSIOM
#define CYBSP_USER_LED5_HSIOM CYBSP_LED_RGB_GREEN_HSIOM
#define CYBSP_LED_RGB_GREEN_IRQ ioss_interrupts_gpio_20_IRQn
#define CYBSP_USER_LED5_IRQ CYBSP_LED_RGB_GREEN_IRQ
#define CYBSP_LED_RGB_BLUE_ENABLED 1U
#define CYBSP_USER_LED4_ENABLED CYBSP_LED_RGB_BLUE_ENABLED
#define CYBSP_LED_RGB_BLUE_PORT GPIO_PRT20
#define CYBSP_USER_LED4_PORT CYBSP_LED_RGB_BLUE_PORT
#define CYBSP_LED_RGB_BLUE_PORT_NUM 20U
#define CYBSP_USER_LED4_PORT_NUM CYBSP_LED_RGB_BLUE_PORT_NUM
#define CYBSP_LED_RGB_BLUE_PIN 5U
#define CYBSP_USER_LED4_PIN CYBSP_LED_RGB_BLUE_PIN
#define CYBSP_LED_RGB_BLUE_NUM 5U
#define CYBSP_USER_LED4_NUM CYBSP_LED_RGB_BLUE_NUM
#define CYBSP_LED_RGB_BLUE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_USER_LED4_DRIVEMODE CYBSP_LED_RGB_BLUE_DRIVEMODE
#define CYBSP_LED_RGB_BLUE_INIT_DRIVESTATE 0
#define CYBSP_USER_LED4_INIT_DRIVESTATE CYBSP_LED_RGB_BLUE_INIT_DRIVESTATE
#ifndef ioss_0_port_20_pin_5_HSIOM
    #define ioss_0_port_20_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_LED_RGB_BLUE_HSIOM ioss_0_port_20_pin_5_HSIOM
#define CYBSP_USER_LED4_HSIOM CYBSP_LED_RGB_BLUE_HSIOM
#define CYBSP_LED_RGB_BLUE_IRQ ioss_interrupts_gpio_20_IRQn
#define CYBSP_USER_LED4_IRQ CYBSP_LED_RGB_BLUE_IRQ
#define CYBSP_LED_RGB_RED_ENABLED 1U
#define CYBSP_USER_LED3_ENABLED CYBSP_LED_RGB_RED_ENABLED
#define CYBSP_LED_RGB_RED_PORT GPIO_PRT20
#define CYBSP_USER_LED3_PORT CYBSP_LED_RGB_RED_PORT
#define CYBSP_LED_RGB_RED_PORT_NUM 20U
#define CYBSP_USER_LED3_PORT_NUM CYBSP_LED_RGB_RED_PORT_NUM
#define CYBSP_LED_RGB_RED_PIN 6U
#define CYBSP_USER_LED3_PIN CYBSP_LED_RGB_RED_PIN
#define CYBSP_LED_RGB_RED_NUM 6U
#define CYBSP_USER_LED3_NUM CYBSP_LED_RGB_RED_NUM
#define CYBSP_LED_RGB_RED_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_USER_LED3_DRIVEMODE CYBSP_LED_RGB_RED_DRIVEMODE
#define CYBSP_LED_RGB_RED_INIT_DRIVESTATE 0
#define CYBSP_USER_LED3_INIT_DRIVESTATE CYBSP_LED_RGB_RED_INIT_DRIVESTATE
#ifndef ioss_0_port_20_pin_6_HSIOM
    #define ioss_0_port_20_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_LED_RGB_RED_HSIOM ioss_0_port_20_pin_6_HSIOM
#define CYBSP_USER_LED3_HSIOM CYBSP_LED_RGB_RED_HSIOM
#define CYBSP_LED_RGB_RED_IRQ ioss_interrupts_gpio_20_IRQn
#define CYBSP_USER_LED3_IRQ CYBSP_LED_RGB_RED_IRQ
#define CYBSP_RXRES_L_ENABLED 1U
#define CYBSP_RADAR_RESET_ENABLED CYBSP_RXRES_L_ENABLED
#define CYBSP_RXRES_L_PORT GPIO_PRT20
#define CYBSP_RADAR_RESET_PORT CYBSP_RXRES_L_PORT
#define CYBSP_RXRES_L_PORT_NUM 20U
#define CYBSP_RADAR_RESET_PORT_NUM CYBSP_RXRES_L_PORT_NUM
#define CYBSP_RXRES_L_PIN 7U
#define CYBSP_RADAR_RESET_PIN CYBSP_RXRES_L_PIN
#define CYBSP_RXRES_L_NUM 7U
#define CYBSP_RADAR_RESET_NUM CYBSP_RXRES_L_NUM
#define CYBSP_RXRES_L_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_RADAR_RESET_DRIVEMODE CYBSP_RXRES_L_DRIVEMODE
#define CYBSP_RXRES_L_INIT_DRIVESTATE 1
#define CYBSP_RADAR_RESET_INIT_DRIVESTATE CYBSP_RXRES_L_INIT_DRIVESTATE
#ifndef ioss_0_port_20_pin_7_HSIOM
    #define ioss_0_port_20_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_RXRES_L_HSIOM ioss_0_port_20_pin_7_HSIOM
#define CYBSP_RADAR_RESET_HSIOM CYBSP_RXRES_L_HSIOM
#define CYBSP_RXRES_L_IRQ ioss_interrupts_gpio_20_IRQn
#define CYBSP_RADAR_RESET_IRQ CYBSP_RXRES_L_IRQ
#define CYBSP_WIFI_SDIO_CMD_ENABLED 1U
#define CYBSP_WIFI_SDIO_CMD_PORT GPIO_PRT21
#define CYBSP_WIFI_SDIO_CMD_PORT_NUM 21U
#define CYBSP_WIFI_SDIO_CMD_PIN 0U
#define CYBSP_WIFI_SDIO_CMD_NUM 0U
#define CYBSP_WIFI_SDIO_CMD_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_WIFI_SDIO_CMD_INIT_DRIVESTATE 1
#ifndef ioss_0_port_21_pin_0_HSIOM
    #define ioss_0_port_21_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_WIFI_SDIO_CMD_HSIOM ioss_0_port_21_pin_0_HSIOM
#define CYBSP_WIFI_SDIO_CMD_IRQ ioss_interrupts_gpio_21_IRQn
#define CYBSP_I2S_TX_SD_ENABLED 1U
#define CYBSP_I2S_TX_SD_PORT GPIO_PRT21
#define CYBSP_I2S_TX_SD_PORT_NUM 21U
#define CYBSP_I2S_TX_SD_PIN 1U
#define CYBSP_I2S_TX_SD_NUM 1U
#define CYBSP_I2S_TX_SD_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_I2S_TX_SD_INIT_DRIVESTATE 1
#ifndef ioss_0_port_21_pin_1_HSIOM
    #define ioss_0_port_21_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_I2S_TX_SD_HSIOM ioss_0_port_21_pin_1_HSIOM
#define CYBSP_I2S_TX_SD_IRQ ioss_interrupts_gpio_21_IRQn
#define CYBSP_I2S_TX_SCK_ENABLED 1U
#define CYBSP_I2S_TX_SCK_PORT GPIO_PRT21
#define CYBSP_I2S_TX_SCK_PORT_NUM 21U
#define CYBSP_I2S_TX_SCK_PIN 2U
#define CYBSP_I2S_TX_SCK_NUM 2U
#define CYBSP_I2S_TX_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_I2S_TX_SCK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_21_pin_2_HSIOM
    #define ioss_0_port_21_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_I2S_TX_SCK_HSIOM ioss_0_port_21_pin_2_HSIOM
#define CYBSP_I2S_TX_SCK_IRQ ioss_interrupts_gpio_21_IRQn
#define CYBSP_I2S_TX_MCK_ENABLED 1U
#define CYBSP_I2S_TX_MCK_PORT GPIO_PRT21
#define CYBSP_I2S_TX_MCK_PORT_NUM 21U
#define CYBSP_I2S_TX_MCK_PIN 3U
#define CYBSP_I2S_TX_MCK_NUM 3U
#define CYBSP_I2S_TX_MCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_I2S_TX_MCK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_21_pin_3_HSIOM
    #define ioss_0_port_21_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_I2S_TX_MCK_HSIOM ioss_0_port_21_pin_3_HSIOM
#define CYBSP_I2S_TX_MCK_IRQ ioss_interrupts_gpio_21_IRQn
#define CYBSP_RSPI_MISO_ENABLED 1U
#define CYBSP_SPI_MISO_ENABLED CYBSP_RSPI_MISO_ENABLED
#define CYBSP_RSPI_MISO_PORT GPIO_PRT21
#define CYBSP_SPI_MISO_PORT CYBSP_RSPI_MISO_PORT
#define CYBSP_RSPI_MISO_PORT_NUM 21U
#define CYBSP_SPI_MISO_PORT_NUM CYBSP_RSPI_MISO_PORT_NUM
#define CYBSP_RSPI_MISO_PIN 4U
#define CYBSP_SPI_MISO_PIN CYBSP_RSPI_MISO_PIN
#define CYBSP_RSPI_MISO_NUM 4U
#define CYBSP_SPI_MISO_NUM CYBSP_RSPI_MISO_NUM
#define CYBSP_RSPI_MISO_DRIVEMODE CY_GPIO_DM_HIGHZ
#define CYBSP_SPI_MISO_DRIVEMODE CYBSP_RSPI_MISO_DRIVEMODE
#define CYBSP_RSPI_MISO_INIT_DRIVESTATE 1
#define CYBSP_SPI_MISO_INIT_DRIVESTATE CYBSP_RSPI_MISO_INIT_DRIVESTATE
#ifndef ioss_0_port_21_pin_4_HSIOM
    #define ioss_0_port_21_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_RSPI_MISO_HSIOM ioss_0_port_21_pin_4_HSIOM
#define CYBSP_SPI_MISO_HSIOM CYBSP_RSPI_MISO_HSIOM
#define CYBSP_RSPI_MISO_IRQ ioss_interrupts_gpio_21_IRQn
#define CYBSP_SPI_MISO_IRQ CYBSP_RSPI_MISO_IRQ
#define CYBSP_RSPI_MOSI_ENABLED 1U
#define CYBSP_SPI_MOSI_ENABLED CYBSP_RSPI_MOSI_ENABLED
#define CYBSP_RSPI_MOSI_PORT GPIO_PRT21
#define CYBSP_SPI_MOSI_PORT CYBSP_RSPI_MOSI_PORT
#define CYBSP_RSPI_MOSI_PORT_NUM 21U
#define CYBSP_SPI_MOSI_PORT_NUM CYBSP_RSPI_MOSI_PORT_NUM
#define CYBSP_RSPI_MOSI_PIN 5U
#define CYBSP_SPI_MOSI_PIN CYBSP_RSPI_MOSI_PIN
#define CYBSP_RSPI_MOSI_NUM 5U
#define CYBSP_SPI_MOSI_NUM CYBSP_RSPI_MOSI_NUM
#define CYBSP_RSPI_MOSI_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_SPI_MOSI_DRIVEMODE CYBSP_RSPI_MOSI_DRIVEMODE
#define CYBSP_RSPI_MOSI_INIT_DRIVESTATE 1
#define CYBSP_SPI_MOSI_INIT_DRIVESTATE CYBSP_RSPI_MOSI_INIT_DRIVESTATE
#ifndef ioss_0_port_21_pin_5_HSIOM
    #define ioss_0_port_21_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_RSPI_MOSI_HSIOM ioss_0_port_21_pin_5_HSIOM
#define CYBSP_SPI_MOSI_HSIOM CYBSP_RSPI_MOSI_HSIOM
#define CYBSP_RSPI_MOSI_IRQ ioss_interrupts_gpio_21_IRQn
#define CYBSP_SPI_MOSI_IRQ CYBSP_RSPI_MOSI_IRQ
#define CYBSP_RSPI_CLK_ENABLED 1U
#define CYBSP_SPI_CLK_ENABLED CYBSP_RSPI_CLK_ENABLED
#define CYBSP_RSPI_CLK_PORT GPIO_PRT21
#define CYBSP_SPI_CLK_PORT CYBSP_RSPI_CLK_PORT
#define CYBSP_RSPI_CLK_PORT_NUM 21U
#define CYBSP_SPI_CLK_PORT_NUM CYBSP_RSPI_CLK_PORT_NUM
#define CYBSP_RSPI_CLK_PIN 6U
#define CYBSP_SPI_CLK_PIN CYBSP_RSPI_CLK_PIN
#define CYBSP_RSPI_CLK_NUM 6U
#define CYBSP_SPI_CLK_NUM CYBSP_RSPI_CLK_NUM
#define CYBSP_RSPI_CLK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_SPI_CLK_DRIVEMODE CYBSP_RSPI_CLK_DRIVEMODE
#define CYBSP_RSPI_CLK_INIT_DRIVESTATE 1
#define CYBSP_SPI_CLK_INIT_DRIVESTATE CYBSP_RSPI_CLK_INIT_DRIVESTATE
#ifndef ioss_0_port_21_pin_6_HSIOM
    #define ioss_0_port_21_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_RSPI_CLK_HSIOM ioss_0_port_21_pin_6_HSIOM
#define CYBSP_SPI_CLK_HSIOM CYBSP_RSPI_CLK_HSIOM
#define CYBSP_RSPI_CLK_IRQ ioss_interrupts_gpio_21_IRQn
#define CYBSP_SPI_CLK_IRQ CYBSP_RSPI_CLK_IRQ
#define CYBSP_RSPI_CS_ENABLED 1U
#define CYBSP_SPI_CS_ENABLED CYBSP_RSPI_CS_ENABLED
#define CYBSP_RSPI_CS_PORT GPIO_PRT21
#define CYBSP_SPI_CS_PORT CYBSP_RSPI_CS_PORT
#define CYBSP_RSPI_CS_PORT_NUM 21U
#define CYBSP_SPI_CS_PORT_NUM CYBSP_RSPI_CS_PORT_NUM
#define CYBSP_RSPI_CS_PIN 7U
#define CYBSP_SPI_CS_PIN CYBSP_RSPI_CS_PIN
#define CYBSP_RSPI_CS_NUM 7U
#define CYBSP_SPI_CS_NUM CYBSP_RSPI_CS_NUM
#define CYBSP_RSPI_CS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_SPI_CS_DRIVEMODE CYBSP_RSPI_CS_DRIVEMODE
#define CYBSP_RSPI_CS_INIT_DRIVESTATE 1
#define CYBSP_SPI_CS_INIT_DRIVESTATE CYBSP_RSPI_CS_INIT_DRIVESTATE
#ifndef ioss_0_port_21_pin_7_HSIOM
    #define ioss_0_port_21_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_RSPI_CS_HSIOM ioss_0_port_21_pin_7_HSIOM
#define CYBSP_SPI_CS_HSIOM CYBSP_RSPI_CS_HSIOM
#define CYBSP_RSPI_CS_IRQ ioss_interrupts_gpio_21_IRQn
#define CYBSP_SPI_CS_IRQ CYBSP_RSPI_CS_IRQ

extern const cy_stc_gpio_pin_config_t CYBSP_OSPI_RAM_CS_config;

#define CYBSP_OSPI_RAM_SS_config CYBSP_OSPI_RAM_CS_config

extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config;
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config;
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config;
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config;
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_CS_config;

#define CYBSP_QSPI_SS_config CYBSP_QSPI_CS_config

extern const cy_stc_gpio_pin_config_t CYBSP_I3C_SCL_config;
extern const cy_stc_gpio_pin_config_t CYBSP_I3C_SDA_config;
extern const cy_stc_gpio_pin_config_t CYBSP_OSPI_RAM_D0_config;
extern const cy_stc_gpio_pin_config_t CYBSP_OSPI_RAM_D1_config;
extern const cy_stc_gpio_pin_config_t CYBSP_OSPI_RAM_D2_config;
extern const cy_stc_gpio_pin_config_t CYBSP_OSPI_RAM_D3_config;
extern const cy_stc_gpio_pin_config_t CYBSP_OSPI_RAM_D4_config;
extern const cy_stc_gpio_pin_config_t CYBSP_OSPI_RAM_D5_config;
extern const cy_stc_gpio_pin_config_t CYBSP_OSPI_RAM_D6_config;
extern const cy_stc_gpio_pin_config_t CYBSP_OSPI_RAM_D7_config;
extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config;
extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config;
extern const cy_stc_gpio_pin_config_t CYBSP_SW1_config;

#define CYBSP_USER_BTN1_config CYBSP_SW1_config
#define CYBSP_USER_BTN_config CYBSP_SW1_config

extern const cy_stc_gpio_pin_config_t CYBSP_EXT_CLK_config;
extern const cy_stc_gpio_pin_config_t CYBSP_I2C_SCL_1V8_config;

#define CYBSP_I2C_SCL_config CYBSP_I2C_SCL_1V8_config

extern const cy_stc_gpio_pin_config_t CYBSP_I2C_SDA_1V8_config;

#define CYBSP_I2C_SDA_config CYBSP_I2C_SDA_1V8_config

extern const cy_stc_gpio_pin_config_t CYBSP_PDM_CLK_config;
extern const cy_stc_gpio_pin_config_t CYBSP_PDM_DATA_config;
extern const cy_stc_gpio_pin_config_t CYBSP_SERIAL_INT_0_config;
extern const cy_stc_gpio_pin_config_t CYBSP_SERIAL_INT_2_config;
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config;
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config;
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config;
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config;
extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config;
extern const cy_stc_gpio_pin_config_t CYBSP_USER_LED2_config;
extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config;
extern const cy_stc_gpio_pin_config_t CYBSP_USER_LED1_config;

#define CYBSP_USER_LED_config CYBSP_USER_LED1_config

extern const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config;
extern const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_PCLK_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_WL_REG_ON_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CLK_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D0_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D1_config;
extern const cy_stc_gpio_pin_config_t CYBSP_I2S_TX_FSYNC_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D2_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D3_config;
extern const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_D0_config;
extern const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_D1_config;
extern const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_D2_config;
extern const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_D3_config;
extern const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_D4_config;
extern const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_D5_config;
extern const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_D6_config;
extern const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_D7_config;
extern const cy_stc_gpio_pin_config_t CYBSP_I2C_SCL_3V3_config;
extern const cy_stc_gpio_pin_config_t CYBSP_I2C_SDA_3V3_config;
extern const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_VSYNC_config;
extern const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_HREF_config;
extern const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_XCLK_config;
extern const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_RESET_config;
extern const cy_stc_gpio_pin_config_t CYBSP_DVP_CAM_PWDN_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
extern const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config;
extern const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config;
extern const cy_stc_gpio_pin_config_t CYBSP_RADAR_INT_config;
extern const cy_stc_gpio_pin_config_t CYBSP_LED_RGB_GREEN_config;

#define CYBSP_USER_LED5_config CYBSP_LED_RGB_GREEN_config

extern const cy_stc_gpio_pin_config_t CYBSP_LED_RGB_BLUE_config;

#define CYBSP_USER_LED4_config CYBSP_LED_RGB_BLUE_config

extern const cy_stc_gpio_pin_config_t CYBSP_LED_RGB_RED_config;

#define CYBSP_USER_LED3_config CYBSP_LED_RGB_RED_config

extern const cy_stc_gpio_pin_config_t CYBSP_RXRES_L_config;

#define CYBSP_RADAR_RESET_config CYBSP_RXRES_L_config

extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CMD_config;
extern const cy_stc_gpio_pin_config_t CYBSP_I2S_TX_SD_config;
extern const cy_stc_gpio_pin_config_t CYBSP_I2S_TX_SCK_config;
extern const cy_stc_gpio_pin_config_t CYBSP_I2S_TX_MCK_config;
extern const cy_stc_gpio_pin_config_t CYBSP_RSPI_MISO_config;

#define CYBSP_SPI_MISO_config CYBSP_RSPI_MISO_config

extern const cy_stc_gpio_pin_config_t CYBSP_RSPI_MOSI_config;

#define CYBSP_SPI_MOSI_config CYBSP_RSPI_MOSI_config

extern const cy_stc_gpio_pin_config_t CYBSP_RSPI_CLK_config;

#define CYBSP_SPI_CLK_config CYBSP_RSPI_CLK_config

extern const cy_stc_gpio_pin_config_t CYBSP_RSPI_CS_config;

#define CYBSP_SPI_CS_config CYBSP_RSPI_CS_config

void init_cycfg_pins(void);

#if defined(__cplusplus)
}
#endif /* defined(__cplusplus) */

#endif /* CYCFG_PINS_H */
