/*******************************************************************************
 * File Name: cycfg_memory.h
 *
 * Description:
 * Memory configuration
 * This file was automatically generated and should not be modified.
 * Configurator Backend 3.60.0
 * device-db 4.34.0.9502
 * mtb-dsl-pse8xxgp 1.2.0.895
 *
 *******************************************************************************
 * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 ******************************************************************************/

#if !defined(CYCFG_MEMORY_H)
#define CYCFG_MEMORY_H

#include "cycfg_notices.h"

#if defined(__cplusplus)
extern "C" {
#endif /* defined(__cplusplus) */

#define vres_0_memory_region_data_0_ENABLED 1U
#define vres_0_memory_region_data_1_ENABLED 1U
#define vres_0_memory_region_data_2_ENABLED 1U
#define vres_0_memory_region_data_3_ENABLED 1U
#define vres_0_memory_region_data_4_ENABLED 1U
#define vres_0_memory_region_data_5_ENABLED 1U
#define vres_0_memory_region_data_6_ENABLED 1U
#define vres_0_memory_region_data_7_ENABLED 1U
#define vres_0_memory_region_data_8_ENABLED 1U
#define vres_0_memory_region_data_9_ENABLED 1U
#define vres_0_memory_region_data_10_ENABLED 1U
#define vres_0_memory_region_data_11_ENABLED 1U
#define vres_0_memory_region_data_12_ENABLED 1U
#define vres_0_memory_region_data_13_ENABLED 1U
#define vres_0_memory_region_data_14_ENABLED 1U
#define vres_0_memory_region_data_15_ENABLED 1U
#define vres_0_memory_region_data_16_ENABLED 1U
#define vres_0_memory_region_data_17_ENABLED 1U
#define vres_0_memory_region_data_18_ENABLED 1U
#define vres_0_memory_region_data_19_ENABLED 1U
#define vres_0_memory_region_data_20_ENABLED 1U
#define vres_0_memory_region_data_21_ENABLED 1U
#define vres_0_memory_region_data_22_ENABLED 1U
#define vres_0_memory_region_data_23_ENABLED 1U
#define vres_0_memory_region_data_24_ENABLED 1U
#define vres_0_memory_0_ENABLED 1U

#if defined(__cplusplus)
}
#endif /* defined(__cplusplus) */

#endif /* CYCFG_MEMORY_H */
