#define MICROPY_HW_BOARD_NAME "phyBOARD-RT1170 Development Kit"
#define MICROPY_HW_MCU_NAME   "MIMXRT1176DVMAA"

#define MICROPY_PY_NETWORK_HOSTNAME_DEFAULT "mpy-phyboard"

// Do not use WFE when waiting for an event.
#define MICROPY_INTERNAL_WFE(TIMEOUT_MS)

// phyBOARD-RT1170 SoM onboard LEDs (red and green from phyCORE SoM)
// Carrier board provides additional RGB LEDs via GPIO
#define MICROPY_HW_LED1_PIN (pin_GPIO_LPSR_07)  // SoM Red LED
#define MICROPY_HW_LED2_PIN (pin_GPIO_LPSR_08)  // SoM Green LED
#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_high(pin))  // LEDs are active low
#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_low(pin))

// phyBOARD carrier board RGB LEDs
#define MICROPY_HW_LED3_PIN (pin_GPIO_AD_14)  // Carrier Red LED
#define MICROPY_HW_LED4_PIN (pin_GPIO_LPSR_13)  // Carrier Green LED

#define MICROPY_HW_NUM_PIN_IRQS (6 * 32)

// Define mapping hardware UART # to logical UART #
// phyBOARD-RT1170 UART interfaces
// LPUART1  -> 0  (GPIO_AD_24/25) - Primary debug/console (SoM)
// LPUART2  -> 1  (GPIO_DISP_B2_10/11/12/13) - Carrier board
// LPUART3  -> 2  (GPIO_AD_30/31) - General purpose (SoM)
// LPUART5  -> 3  (GPIO_AD_28/29) - Expansion (SoM)
// LPUART6  -> 4  (GPIO_EMC_B1_40/41) - Console UART (FT2232H - Carrier)
// LPUART7  -> 5  (GPIO_DISP_B2_06/07) - General purpose (SoM)
// LPUART8  -> 6  (GPIO_AD_02/03/04/05) - RS-232 (Carrier)

#define MICROPY_HW_UART_NUM     (sizeof(uart_index_table) / sizeof(uart_index_table)[0])
#define MICROPY_HW_UART_INDEX   { 1, 2, 3, 5, 6, 7, 8 }

#define IOMUX_TABLE_UART \
    { IOMUXC_GPIO_AD_24_LPUART1_TXD }, { IOMUXC_GPIO_AD_25_LPUART1_RXD }, \
    { IOMUXC_GPIO_DISP_B2_10_LPUART2_TXD }, { IOMUXC_GPIO_DISP_B2_11_LPUART2_RXD }, \
    { IOMUXC_GPIO_AD_30_LPUART3_TXD }, { IOMUXC_GPIO_AD_31_LPUART3_RXD }, \
    { 0 }, { 0 }, \
    { IOMUXC_GPIO_AD_28_LPUART5_TXD }, { IOMUXC_GPIO_AD_29_LPUART5_RXD }, \
    { IOMUXC_GPIO_EMC_B1_40_LPUART6_TXD }, { IOMUXC_GPIO_EMC_B1_41_LPUART6_RXD }, \
    { IOMUXC_GPIO_DISP_B2_06_LPUART7_TXD }, { IOMUXC_GPIO_DISP_B2_07_LPUART7_RXD }, \
    { IOMUXC_GPIO_AD_02_LPUART8_TXD }, { IOMUXC_GPIO_AD_03_LPUART8_RXD }, \
    { 0 }, { 0 }, \
    { 0 }, { 0 }, \
    { 0 }, { 0 }, \
    { 0 }, { 0 },

#define IOMUX_TABLE_UART_CTS_RTS \
    { 0 }, { 0 }, \
    { IOMUXC_GPIO_DISP_B2_12_LPUART2_CTS_B }, { IOMUXC_GPIO_DISP_B2_13_LPUART2_RTS_B }, \
    { 0 }, { 0 }, \
    { 0 }, { 0 }, \
    { 0 }, { 0 }, \
    { 0 }, { 0 }, \
    { 0 }, { 0 }, \
    { IOMUXC_GPIO_AD_04_LPUART8_CTS_B }, { IOMUXC_GPIO_AD_05_LPUART8_RTS_B }, \
    { 0 }, { 0 }, \
    { 0 }, { 0 }, \
    { 0 }, { 0 }, \
    { 0 }, { 0 },

// Define the mapping hardware SPI # to logical SPI #
// phyCORE SoM basic SPI interfaces available on connector
// LPSPI1  ->  0  (GPIO_AD_28/29/30/31)
// LPSPI2  ->  1  (GPIO_AD_24/25/26/27)

#define MICROPY_HW_SPI_INDEX { 1, 2 }

#define IOMUX_TABLE_SPI \
    { IOMUXC_GPIO_AD_28_LPSPI1_SCK }, { IOMUXC_GPIO_AD_29_LPSPI1_PCS0 }, \
    { IOMUXC_GPIO_AD_30_LPSPI1_SOUT }, { IOMUXC_GPIO_AD_31_LPSPI1_SIN }, \
    { IOMUXC_GPIO_AD_24_LPSPI2_SCK }, { IOMUXC_GPIO_AD_25_LPSPI2_PCS0 }, \
    { IOMUXC_GPIO_AD_26_LPSPI2_SOUT }, { IOMUXC_GPIO_AD_27_LPSPI2_SIN }, \
    { 0 }, { 0 }, \
    { 0 }, { 0 }, \
    { 0 }, { 0 }, \
    { 0 }, { 0 }, \
    { 0 }, { 0 }, \
    { 0 }, { 0 }, \
    { 0 }, { 0 }, \
    { 0 }, { 0 },


#define DMA_REQ_SRC_RX { 0, kDmaRequestMuxLPSPI1Rx, kDmaRequestMuxLPSPI2Rx, \
                         kDmaRequestMuxLPSPI3Rx, kDmaRequestMuxLPSPI4Rx }

#define DMA_REQ_SRC_TX { 0, kDmaRequestMuxLPSPI1Tx, kDmaRequestMuxLPSPI2Tx, \
                         kDmaRequestMuxLPSPI3Tx, kDmaRequestMuxLPSPI4Tx }

// Define the mapping hardware I2C # to logical I2C #
// phyBOARD-RT1170 I2C interfaces
// LPI2C1 ->    0  (GPIO_AD_32/33) - EEPROM (SoM)
// LPI2C2 ->    1  (GPIO_AD_18/19) - EEPROM + Accelerometer (Carrier)
// LPI2C3 ->    2  (GPIO_DISP_B2_10/11) - Reserved (SoM)
// LPI2C5 ->    3  (GPIO_LPSR_08/09, GPIO_AD_26/27) - Audio Codec + Accelerometer (Carrier)

#define MICROPY_HW_I2C_INDEX   { 1, 2, 3, 5 }

#define IOMUX_TABLE_I2C \
    { IOMUXC_GPIO_AD_32_LPI2C1_SCL }, { IOMUXC_GPIO_AD_33_LPI2C1_SDA }, \
    { IOMUXC_GPIO_AD_18_LPI2C2_SCL }, { IOMUXC_GPIO_AD_19_LPI2C2_SDA }, \
    { IOMUXC_GPIO_DISP_B2_10_LPI2C3_SCL }, { IOMUXC_GPIO_DISP_B2_11_LPI2C3_SDA }, \
    { 0 }, { 0 }, \
    { IOMUXC_GPIO_LPSR_08_LPI2C5_SDA }, { IOMUXC_GPIO_LPSR_09_LPI2C5_SCL }, \
    { 0 }, { 0 },

#define MICROPY_HW_CAN1_NAME "CAN1"
#define MICROPY_HW_NUM_CAN (1)
#define MICROPY_HW_CAN_INDEX { 3 }
#define MICROPY_HW_NUM_CAN_IRQS (1)

#define IOMUX_TABLE_CAN \
    { 0 }, { 0 }, \
    { 0 }, { 0 }, \
    { IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX }, { IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX },

#define MICROPY_PY_MACHINE_I2S (1)
#define MICROPY_HW_I2S_NUM (1)
#define I2S_CLOCK_MUX { 0, kCLOCK_Root_Sai1, kCLOCK_Root_Sai2, kCLOCK_Root_Sai3, kCLOCK_Root_Sai4 }
#define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx, kDmaRequestMuxSai2Rx, kDmaRequestMuxSai3Rx, kDmaRequestMuxSai4Rx }
#define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx, kDmaRequestMuxSai2Tx, kDmaRequestMuxSai3Tx, kDmaRequestMuxSai4Tx }
#define I2S_WM8960_RX_MODE  (1)
#define I2S_AUDIO_PLL_CLOCK (4U)
#define DMAMUX DMAMUX0

#define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \
    { \
        .hw_id = _hwid, \
        .fn = _fn, \
        .mode = _mode, \
        .name = MP_QSTR_##_pin, \
        .iomux = {_iomux}, \
    }

#define I2S_GPIO_MAP \
    { \
        I2S_GPIO(1, MCK, TX, GPIO_AD_17, IOMUXC_GPIO_AD_17_SAI1_MCLK), \
        I2S_GPIO(1, SCK, RX, GPIO_AD_19, IOMUXC_GPIO_AD_19_SAI1_RX_BCLK), \
        I2S_GPIO(1, WS, RX, GPIO_AD_18, IOMUXC_GPIO_AD_18_SAI1_RX_SYNC), \
        I2S_GPIO(1, SD, RX, GPIO_AD_20, IOMUXC_GPIO_AD_20_SAI1_RX_DATA00),  \
        I2S_GPIO(1, SCK, TX, GPIO_AD_22, IOMUXC_GPIO_AD_22_SAI1_TX_BCLK), \
        I2S_GPIO(1, WS, TX, GPIO_AD_23, IOMUXC_GPIO_AD_23_SAI1_TX_SYNC),  \
        I2S_GPIO(1, SD, TX, GPIO_AD_21, IOMUXC_GPIO_AD_21_SAI1_TX_DATA00), \
    }

// USDHC1 (SDCARD)
#define MICROPY_PY_MACHINE_SDCARD 0
#if MICROPY_PY_MACHINE_SDCARD
#define USDHC_DUMMY_PIN NULL, 0
#define MICROPY_USDHC1 \
    { \
        .cmd = {GPIO_SD_B1_00_USDHC1_CMD}, \
        .clk = { GPIO_SD_B1_01_USDHC1_CLK }, \
        .cd_b = { USDHC_DUMMY_PIN }, \
        .data0 = { GPIO_SD_B1_02_USDHC1_DATA0 }, \
        .data1 = { GPIO_SD_B1_03_USDHC1_DATA1 }, \
        .data2 = { GPIO_SD_B1_04_USDHC1_DATA2 }, \
        .data3 = { GPIO_SD_B1_05_USDHC1_DATA3 }, \
    }
#define USDHC_DATA3_PULL_DOWN_ON_BOARD    (1)
#endif

// Network definitions

// phyBOARD-RT1170 Dual Ethernet configuration
// Port 0: KSZ8081 100Mbps RMII PHY on carrier board (PBA-C-26)
// Port 1: DP83867 1Gbps RGMII PHY on phyCORE SoM

// Primary Ethernet (100M RMII) - KSZ8081 on carrier board
#define ENET_PHY_ADDRESS    (1)  // KSZ8081 PHY address 001b
#define ENET_PHY             KSZ8081
#define ENET_PHY_OPS         phyksz8081_ops

// ENET RMII pin configuration - connected to carrier board KSZ8081
#define IOMUX_TABLE_ENET \
    { IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00, 0, 0x06u }, \
    { IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01, 0, 0x06u }, \
    { IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN, 0, 0x06u }, \
    { IOMUXC_GPIO_DISP_B2_02_ENET_TX_DATA00, 0, 0x02u }, \
    { IOMUXC_GPIO_DISP_B2_03_ENET_TX_DATA01, 0, 0x02u }, \
    { IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN, 0, 0x06u }, \
    { IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK, 1, 0x03u }, \
    { IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER, 0, 0x06u }, \
    { IOMUXC_GPIO_AD_33_ENET_MDIO, 0, 0x06u }, \
    { IOMUXC_GPIO_AD_32_ENET_MDC, 0, 0x06u },

// Secondary Ethernet (1G RGMII) - DP83867 on phyCORE SoM
#define ENET_1_PHY_ADDRESS     (0)
#define ENET_1_PHY             DP83867
#define ENET_1_PHY_OPS         phydp83867_ops

// ENET_1G RGMII pin configuration - full RGMII pins for Gigabit operation
#define IOMUX_TABLE_ENET_1 \
    { IOMUXC_GPIO_DISP_B1_00_ENET_1G_RX_EN, 0, 0x08U }, \
    { IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_CLK, 0, 0x08U }, \
    { IOMUXC_GPIO_DISP_B1_02_ENET_1G_RX_DATA00, 0, 0x08U }, \
    { IOMUXC_GPIO_DISP_B1_03_ENET_1G_RX_DATA01, 0, 0x08U }, \
    { IOMUXC_GPIO_DISP_B1_04_ENET_1G_RX_DATA02, 0, 0x08U }, \
    { IOMUXC_GPIO_DISP_B1_05_ENET_1G_RX_DATA03, 0, 0x08U }, \
    { IOMUXC_GPIO_DISP_B1_06_ENET_1G_TX_DATA03, 0, 0x0CU }, \
    { IOMUXC_GPIO_DISP_B1_07_ENET_1G_TX_DATA02, 0, 0x0CU }, \
    { IOMUXC_GPIO_DISP_B1_08_ENET_1G_TX_DATA01, 0, 0x0CU }, \
    { IOMUXC_GPIO_DISP_B1_09_ENET_1G_TX_DATA00, 0, 0x0CU }, \
    { IOMUXC_GPIO_DISP_B1_10_ENET_1G_TX_EN, 0, 0x0CU }, \
    { IOMUXC_GPIO_DISP_B1_11_ENET_1G_TX_CLK_IO, 0, 0x0CU }, \
    { IOMUXC_GPIO_EMC_B2_20_ENET_1G_MDIO, 0, 0x06u }, \
    { IOMUXC_GPIO_EMC_B2_19_ENET_1G_MDC, 0, 0x06u },


// --- SEMC --- //
#define MIMXRT_IOMUXC_SEMC_DATA00 IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00
#define MIMXRT_IOMUXC_SEMC_DATA01 IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01
#define MIMXRT_IOMUXC_SEMC_DATA02 IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02
#define MIMXRT_IOMUXC_SEMC_DATA03 IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03
#define MIMXRT_IOMUXC_SEMC_DATA04 IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04
#define MIMXRT_IOMUXC_SEMC_DATA05 IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05
#define MIMXRT_IOMUXC_SEMC_DATA06 IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06
#define MIMXRT_IOMUXC_SEMC_DATA07 IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07
#define MIMXRT_IOMUXC_SEMC_DATA08 IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08
#define MIMXRT_IOMUXC_SEMC_DATA09 IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09
#define MIMXRT_IOMUXC_SEMC_DATA10 IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10
#define MIMXRT_IOMUXC_SEMC_DATA11 IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11
#define MIMXRT_IOMUXC_SEMC_DATA12 IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12
#define MIMXRT_IOMUXC_SEMC_DATA13 IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13
#define MIMXRT_IOMUXC_SEMC_DATA14 IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14
#define MIMXRT_IOMUXC_SEMC_DATA15 IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15

#define MIMXRT_IOMUXC_SEMC_ADDR00 IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00
#define MIMXRT_IOMUXC_SEMC_ADDR01 IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01
#define MIMXRT_IOMUXC_SEMC_ADDR02 IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02
#define MIMXRT_IOMUXC_SEMC_ADDR03 IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03
#define MIMXRT_IOMUXC_SEMC_ADDR04 IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04
#define MIMXRT_IOMUXC_SEMC_ADDR05 IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05
#define MIMXRT_IOMUXC_SEMC_ADDR06 IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06
#define MIMXRT_IOMUXC_SEMC_ADDR07 IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07
#define MIMXRT_IOMUXC_SEMC_ADDR08 IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08
#define MIMXRT_IOMUXC_SEMC_ADDR09 IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09
#define MIMXRT_IOMUXC_SEMC_ADDR10 IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10
#define MIMXRT_IOMUXC_SEMC_ADDR11 IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11
#define MIMXRT_IOMUXC_SEMC_ADDR12 IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12

#define MIMXRT_IOMUXC_SEMC_BA0 IOMUXC_GPIO_EMC_B1_21_SEMC_BA0
#define MIMXRT_IOMUXC_SEMC_BA1 IOMUXC_GPIO_EMC_B1_22_SEMC_BA1
#define MIMXRT_IOMUXC_SEMC_CAS IOMUXC_GPIO_EMC_B1_24_SEMC_CAS
#define MIMXRT_IOMUXC_SEMC_RAS IOMUXC_GPIO_EMC_B1_25_SEMC_RAS
#define MIMXRT_IOMUXC_SEMC_CLK IOMUXC_GPIO_EMC_B1_26_SEMC_CLK
#define MIMXRT_IOMUXC_SEMC_CKE IOMUXC_GPIO_EMC_B1_27_SEMC_CKE
#define MIMXRT_IOMUXC_SEMC_WE IOMUXC_GPIO_EMC_B1_28_SEMC_WE
#define MIMXRT_IOMUXC_SEMC_DM00 IOMUXC_GPIO_EMC_B1_08_SEMC_DM00
#define MIMXRT_IOMUXC_SEMC_DM01 IOMUXC_GPIO_EMC_B1_38_SEMC_DM01
#define MIMXRT_IOMUXC_SEMC_DQS IOMUXC_GPIO_EMC_B1_39_SEMC_DQS

#define MIMXRT_IOMUXC_SEMC_CS0 IOMUXC_GPIO_EMC_B1_29_SEMC_CS0

#define MIMXRT_IOMUXC_SEMC_DATA16 IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16
#define MIMXRT_IOMUXC_SEMC_DATA17 IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17
#define MIMXRT_IOMUXC_SEMC_DATA18 IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18
#define MIMXRT_IOMUXC_SEMC_DATA19 IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19
#define MIMXRT_IOMUXC_SEMC_DATA20 IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20
#define MIMXRT_IOMUXC_SEMC_DATA21 IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21
#define MIMXRT_IOMUXC_SEMC_DATA22 IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22
#define MIMXRT_IOMUXC_SEMC_DATA23 IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23
#define MIMXRT_IOMUXC_SEMC_DM02   IOMUXC_GPIO_EMC_B2_08_SEMC_DM02

#define MIMXRT_IOMUXC_SEMC_DATA24 IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24
#define MIMXRT_IOMUXC_SEMC_DATA25 IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25
#define MIMXRT_IOMUXC_SEMC_DATA26 IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26
#define MIMXRT_IOMUXC_SEMC_DATA27 IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27
#define MIMXRT_IOMUXC_SEMC_DATA28 IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28
#define MIMXRT_IOMUXC_SEMC_DATA29 IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29
#define MIMXRT_IOMUXC_SEMC_DATA30 IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30
#define MIMXRT_IOMUXC_SEMC_DATA31 IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31
#define MIMXRT_IOMUXC_SEMC_DM03   IOMUXC_GPIO_EMC_B2_17_SEMC_DM03
#define MIMXRT_IOMUXC_SEMC_DQS4   IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4

#if MICROPY_PY_MACHINE_I2S
#define MICROPY_BOARD_ROOT_POINTERS \
    struct _machine_i2s_obj_t *machine_i2s_obj[MICROPY_HW_I2S_NUM];
#endif

// AUTOGENERATED by update.py from copier
#define MICROPY_HW_USB_CDC_NUM (2)
#define MICROPY_HW_USB_MSC (0)
#define MICROPY_HW_USB_HID (0)

#define MICROPY_HW_USB_MANUFACTURER_STRING      "PHYTEC"
#define MICROPY_HW_USB_PRODUCT_HS_STRING        "phyBOARD-RT1170 Development Kit"
#define MICROPY_HW_USB_PRODUCT_FS_STRING        "phyBOARD-RT1170 Development Kit"
#define MICROPY_HW_USB_CONFIGURATION_HS_STRING  "phyBOARD Config"
#define MICROPY_HW_USB_INTERFACE_HS_STRING      "phyBOARD Interface"
#define MICROPY_HW_USB_CONFIGURATION_FS_STRING  "phyBOARD Config"
#define MICROPY_HW_USB_INTERFACE_FS_STRING      "phyBOARD Interface"

#define MBOOT_USBD_MANUFACTURER_STRING "PHYTEC"
#define MBOOT_USBD_PRODUCT_STRING      "phyBOARD Boot"

// phyBOARD-RT1170 Development Kit hardware features

// Onboard EEPROM (M24C32 - 32Kbit)
#define MICROPY_HW_EEPROM_I2C_BUS   (0)  // On LPI2C1 (SoM)
#define MICROPY_HW_EEPROM_ADDR      (0x50)

// Carrier board peripherals
// Audio Codec: TLV320AIC3110 on LPI2C5 (I2C address: 0x18)
// Accelerometer: ICM-40627 on LPI2C2 (I2C address: 0x6B)
// CAN Interface: CAN3 (GPIO_LPSR_00/01)
// RS-232 Serial: LPUART8 (GPIO_AD_02/03/04/05)
// User Button: GPIO_AD_35
// RGB LEDs: GPIO_AD_14 (red), GPIO_LPSR_13 (green)
// microSD Card Slot: USDHC1
// M.2 Connector (Key E): WiFi/Bluetooth modules

// Basic ADC channels available on connector
#define MICROPY_HW_ADC_NUM_CHANNELS (16)  // GPIO_AD domain pins
