LiteX Notes

Notes from building FPGA SoCs with LiteX.

LiteX main developer · Enjoy-Digital

Notes on building open-source FPGA SoCs with LiteX: cores, peripherals, simulation, and the occasional debugging story.

Mostly things I wanted to write down while they were still fresh. 🙂

Recent

LiteX + MCP: who needs hands on the bench?

3 November 2026·2165 words·11 mins

Methodology Litex Ai Agents Mcp Fpga Litescope Ecp5 Methodology

The follow-up to FPGA development in the AI era: the LiteX tools now also come as an MCP server. What it is, what a real board taught it, what 132 agent runs say about when it helps, and what happened when a strong model delegated the bench to a small one.

USB3-PIPE on Gowin: fitting a USB 3 device into a slower fabric, from the Tang Mega 138K to the SLogic16U3

30 October 2026·1980 words·10 mins

Hardware Litex Fpga Usb3 Usb3-Pipe Gowin Gw5a Gtr12 Liteiclink Sipeed Slogic16u3

Porting USB3-PIPE to Gowin GW5A FPGAs: why the Artix7/UltraScale+ fabrics and Vivado made the first two steps easier, what we had to cut and restructure to close timing on Gowin, the synthesis and place-and-route issues we hit, the 5Gbps results on the Tang Mega 138K Pro, and the open USB 3 gateware for the SLogic16U3.

USB3-PIPE at 10Gbps: SuperSpeedPlus on a second-hand Kintex UltraScale+ card

30 October 2026·1923 words·10 mins

Hardware Litex Fpga Usb3 Usb3-Pipe Superspeedplus Ultrascale+ Gty Transceivers Xcku3p

How USB3-PIPE got from 5Gbps to 10Gbps: what USB 3.2 Gen 2 changes, why we built it in simulation before touching hardware, the four bring-up milestones on an Alibaba Cloud XCKU3P card, what only the hardware could show, and the measured throughput.

USB3-PIPE: USB 3 SuperSpeed in the FPGA fabric, from a 2019 link to a 5Gbps device

30 October 2026·2645 words·13 mins

Hardware Litex Fpga Usb3 Usb3-Pipe Artix7 Gtp Transceivers Liteiclink Acorn

How USB3-PIPE went from a 2019 link-training experiment to a complete USB 3 SuperSpeed device stack in the FPGA fabric: why it stalled, what following the spec really involves, how the work restarted, the hardware issues found on the Acorn’s Artix7 GTP, and the measured results.

TriXium, part 3: from Bonsai to Bonsai 2, porting an FPGA LLM design to a hybrid architecture

30 October 2026·2322 words·11 mins

Hardware Litex Fpga Llm Ternary Deltanet Qwen3.5 Bonsai Trixium

Part 3 of TriXium: porting a design built for the Qwen3-based Bonsai models to the Qwen3.5 hybrid Bonsai 2 family. The CPU path first, token-exact in two days, then one fixed-function unit at a time, and the 2B and 4B on the small boards two days after their release.

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