I am an Electronics and Communication Engineering sophomore at MIT Manipal with interests in digital IC design, RTL development using Verilog, and FPGA-based system implementation. My work includes hands-on digital communication blocks, sensor interfacing systems, and basic display interfacing on FPGA. I focus on building strong fundamentals across digital electronics, computer architecture, and EM theory, with an emphasis on writing synthesizable RTL and understanding real hardware behavior beyond simulation.
| Repository | Description | Core Concepts | Technologies |
|---|---|---|---|
| MPU_GONIOMETER | Orientation and angle measurement system using MPU IMU sensors | Sensor interfacing, signal interpretation, embedded systems | C, IMU |
| UART Rx/Tx for Tang Nano 9K FPGA | UART receiver and transmitter implemented and tested on FPGA | FSM design, serial communication, timing control | Verilog, FPGA |
| ST7789-Graphics-driver-for-FPGAs | Driving an ST7789 display using FPGA with supporting image conversion pipeline | Display interfacing, data formatting, timing control | Verilog, FPGA, JS |
| Basic-Tutorial-Blocks | Collection of simple Verilog modules (multipliers, registers, etc.) for learning and experimentation | RTL fundamentals, datapath design | Verilog |
| Area | Details |
|---|---|
| Digital Design | RTL design in Verilog, FSMs, timing-aware logic |
| Chip Design | Introductory understanding of RTL-to-synthesis flow |
| Embedded Systems | Sensor interfacing, data acquisition |
| RF & EM | Antenna design fundamentals |
| Energy Systems | Piezoelectric energy harvesting research |
I have research exposure in piezoelectric energy harvesting and antenna design, strengthening my understanding of applied electromagnetics and hardware-oriented problem solving.
