Linux make Command with Practical Examples

Introduction

In this lab, you will learn how to use the Linux make command to automate the process of building and compiling software from source code. You will start by understanding the purpose and syntax of the make command, then create a simple Makefile and compile a C program. Finally, you will explore the use of Makefile variables and targets.

The lab covers essential skills in the Scripting and Programming domain, providing practical examples and hands-on experience with the make command. The steps outlined in the lab will guide you through the process of setting up a Makefile, managing dependencies, and efficiently compiling your C program.

Linux Commands Cheat Sheet

Understand the Purpose and Syntax of the make Command

In this step, you will learn about the purpose and syntax of the make command in Linux. The make command is a tool used to automate the process of building and compiling software from source code.

First, let's understand the purpose of the make command. The make command reads a file called a "Makefile" that contains instructions on how to build a program or project. The Makefile specifies the dependencies between the different source files, as well as the commands needed to compile and link the program.

The basic syntax of the make command is:

make [target]

Where [target] is the name of the target you want to build. If no target is specified, make will build the first target defined in the Makefile.

Here's an example of a simple Makefile:

all: hello

hello: hello.c
    gcc -o hello hello.c

In this example, the all target depends on the hello target, which in turn depends on the hello.c source file. When you run make, it will compile the hello.c file and create the hello executable.

Let's try it out. First, create the hello.c file:

nano hello.c

Add the following content:

#include <stdio.h>

int main() {
    printf("Hello, world!\n");
    return 0;
}

Save and exit the editor.

Now, run the make command:

make

Example output:

gcc -o hello hello.c

The make command has compiled the hello.c file and created the hello executable.

Create a Simple Makefile and Compile a C Program

In this step, you will learn how to create a simple Makefile and use it to compile a C program.

First, let's create a new C file called hello.c in the ~/project directory:

nano ~/project/hello.c

Add the following content to the file:

#include <stdio.h>

int main() {
    printf("Hello, World!\n");
    return 0;
}

Save and exit the editor.

Now, let's create a simple Makefile in the ~/project directory:

nano ~/project/Makefile

Add the following content to the Makefile:

all: hello

hello: hello.c
    gcc -o hello hello.c

This Makefile defines a target called hello that depends on the hello.c file. The gcc command is used to compile the hello.c file and create the hello executable.

To compile the program using the Makefile, run the following command in the ~/project directory:

make

Example output:

gcc -o hello hello.c

The make command has compiled the hello.c file and created the hello executable.

You can now run the hello program:

./hello

Example output:

Hello, World!

The make command has successfully compiled the C program using the Makefile.

Use Makefile Variables and Targets

In this step, you will learn how to use variables and targets in a Makefile to make your build process more flexible and maintainable.

Let's start by modifying the Makefile we created in the previous step. Open the Makefile in the ~/project directory:

nano ~/project/Makefile

Update the Makefile with the following content:

CC = gcc
CFLAGS = -Wall -Wextra -O2

all: hello

hello: hello.c
    $(CC) $(CFLAGS) -o hello hello.c

In this updated Makefile, we've introduced two variables:

1. CC: This variable stores the name of the C compiler to use. We've set it to gcc.
2. CFLAGS: This variable stores the compilation flags to use. We've set it to -Wall -Wextra -O2, which enables additional compiler warnings and optimizes the compiled code.

We've also updated the compilation command to use these variables:

    $(CC) $(CFLAGS) -o hello hello.c

This makes the Makefile more flexible, as you can easily change the compiler or compilation flags by modifying the variable values.

Now, let's try building the hello program again using the updated Makefile:

make

Example output:

gcc -Wall -Wextra -O2 -o hello hello.c

The make command has used the variables defined in the Makefile to compile the hello.c file.

You can also define additional targets in the Makefile. For example, let's add a clean target to remove the compiled hello executable:

CC = gcc
CFLAGS = -Wall -Wextra -O2

all: hello

hello: hello.c
    $(CC) $(CFLAGS) -o hello hello.c

clean:
    rm -f hello

Now, you can run make clean to remove the hello executable:

make clean

Example output:

rm -f hello

The make clean command has removed the hello executable.

Summary

In this lab, you learned about the purpose and syntax of the make command in Linux, which is used to automate the process of building and compiling software from source code. You created a simple Makefile and used it to compile a C program, understanding how to define dependencies and build targets. Additionally, you explored the use of Makefile variables and targets to make the build process more flexible and reusable.

Linux Commands Cheat Sheet