Balanced ternary · in real hardware

Performance and efficiency in the third Millennium

A CPU that thinks in −1, 0, +1 — not just 0 and 1.

The 5500FP is a 24-trit RISC processor running on genuine ±3.3V ternary signal levels, not an emulation layer over binary logic. Built for supercomputing, AI and brain-simulation workloads that outgrow binary — the same architecture also lays the groundwork for edge and low-power applications.

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24-trit word · one live 5500FP register −1  0  +1
5500FP ternary CPU board
5500FP Ternary CPU
Why it's built this way

Ternary isn't a novelty here. It's the architecture.

Native hardware execution

Run entire operating systems, complex algorithms and computational models natively in a pure three-state environment — every layer of the stack handled directly in ternary, with no binary translation underneath.

Higher information density

Each trit carries roughly 1.58 bits of information, enabling compact data structures for finite automata, formal parsing and multi-valued routing — expressed in their natural logic paradigm, not forced into binary.

Optimized for AI & ML

Ternary logic maps directly onto ternary neural networks and modern LLM weight quantization (−1, 0, +1). Executing these natively removes the binary-emulation bottleneck for symbolic AI and alternative ML models.

The case for ternary

Moore's law stopped doing the heavy lifting.

As transistors approach atomic scale, energy consumption and heat generation — not raw transistor count — have become the limiting factors. Ternary systems raise the information density per connector, so the same physical bus carries more state.

Ternary computing has mostly stayed an academic research topic since binary became the mainstream default in the 1970s. Building it forward means building the infrastructure and tooling almost from scratch — but it also means skipping decades of binary legacy constraints and designing directly for what's next.

1.58 bit information carried per trit (log₂3)
24 trit 8 fewer wires than 32-bit binary≈6.0 bit more capacity+278.13 billion representable states
5500FP three-state signal board detail
Available for preorder

5500FP — the CPU, not a simulation of one

A 24-trit balanced-ternary RISC processor — the hardware realization of our ternary architecture, with real ±3.3V ternary signal levels on the external buses.

ArchitectureRISC
Word size24 trit
Addressable memory31G tryte
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Where ternary wins

Built for problems that are naturally multi-valued.

What we do

Research, silicon, tools and documentation — one small team.

Focus

Research & design

Downloads

Software tooling

Hardware

5500FP processor

Real hardware with a real ternary processor inside.

Open for preorder
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Press & research

They're talking about it.

Preprint

"5500FP: A 24-Trit Balanced Ternary RISC Processor," published on Zenodo — the full technical account of the architecture and its FPGA implementation.

Read on Zenodo ↗

ISMVL 2026, Sendai

Presented at the 35th International Workshop on Post-Binary ULSI Systems, held alongside the IEEE International Symposium on Multiple-Valued Logic.

Workshop page ↗
In the press