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[BUG] FSQRT.S with RDN rounds upward by one ULP
Type:BugFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemStatus: Open.#3396 In openhwgroup/cva6;[BUG] FDIV.S with RDN rounds upward by one ULP
Type:BugFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemStatus: Open.#3395 In openhwgroup/cva6;[BUG] CVA6 reports Store/AMO page fault for LR.W instead of Load page fault
Type:BugFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemStatus: Open.#3394 In openhwgroup/cva6;[BUG] VCU118 constraint file, TX and RX reversed for UART
Type:BugFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemStatus: Open.#3392 In openhwgroup/cva6;[BUG] AMO to invalid physical address retires without raising Store/AMO access fault
Type:BugFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemStatus: Open.#3390 In openhwgroup/cva6;[BUG] HLV load misses a preceding store and reads stale data after a TLB-miss retry
Type:BugFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemStatus: Open.#3389 In openhwgroup/cva6;[BUG] csr_regfile: dcsr.prv is not WARL-legalized on write; dret can set priv_lvl to an unimplemented encoding (2'b10)
Component:RTLFor issues in the RTL (e.g. for files in the rtl directory)For issues in the RTL (e.g. for files in the rtl directory)Type:BugFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemStatus: Open.#3383 In openhwgroup/cva6;[BUG] csr_regfile: mtval zeroing tests ex_i.cause[GPLEN-1] instead of [XLEN-1]; interrupt traps leave instruction bits in mtval/stval
Component:RTLFor issues in the RTL (e.g. for files in the rtl directory)For issues in the RTL (e.g. for files in the rtl directory)Type:BugFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemStatus: Open.#3379 In openhwgroup/cva6;[BUG] Verilator test harness can crash during teardown after terminal result marker
Component:VerifFor issues in the verification environment or test cases (e.g. for testbench, C code, etc.)For issues in the verification environment or test cases (e.g. for testbench, C code, etc.)Type:BugFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemStatus: Open.#3376 In openhwgroup/cva6;Question about hardware performance counters and Linux
perf statsupportType:QuestionFor general questionsFor general questionsStatus: Open.#3374 In openhwgroup/cva6;[BUG] Slot-1 AES can overwrite slot-0 branch one-cycle data and hang superscalar CVA6
Component:RTLFor issues in the RTL (e.g. for files in the rtl directory)For issues in the RTL (e.g. for files in the rtl directory)Type:BugFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemStatus: Open.#3370 In openhwgroup/cva6;[BUG] Superscalar no-RVC frontend can pop an empty instruction queue FIFO
Type:BugFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemFor bugs in the RTL, Documentation, Verification environment or Tool and Build systemStatus: Open.#3369 In openhwgroup/cva6;
