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Default build scripts for boards do not produce yosys.log and next.log

enhancementNew feature or requestNew feature or request

Status: Open.

#287 In sylefeb/Silice;

· sylefeb opened on Dec 30, 2025

Clocks and PLLs

Status: Open.

#282 In sylefeb/Silice;

· sylefeb opened on Jul 3, 2025

Combinational cycle wrongly detected on array assignement

enhancementNew feature or requestNew feature or request

Status: Open.

#277 In sylefeb/Silice;

· Daemiryon opened on Apr 22, 2025

incorrect verilog code genereted

Status: Open.

#276 In sylefeb/Silice;

· Daemiryon opened on Apr 15, 2025

Enhancement of declaration of and usage of always assignments

Status: Open.

#269 In sylefeb/Silice;

· rob-ng15 opened on Apr 15, 2024

$$ directives in board file Verilog are not ignored in code disabled by preprocessor test or /* */

enhancementNew feature or requestNew feature or request

Status: Open.

#268 In sylefeb/Silice;

· FPGAEveryday opened on Apr 13, 2024

Enhancement of declaration of bram/brom/simple_dualport_bram/dualport_bram

enhancementNew feature or requestNew feature or request

Status: Open.

#267 In sylefeb/Silice;

· rob-ng15 opened on Apr 8, 2024

uart_tx and uart_rx seem to have wrong direction in the Verilog framework file for the ECPIX5-Board

Status: Open.

#254 In sylefeb/Silice;

· at91rm9200 opened on Aug 19, 2023

Error initialising bram not brom

Status: Open.

#251 In sylefeb/Silice;

· rob-ng15 opened on May 12, 2023

Unused states that remain and cycles that could be avoided

Status: Open.

#248 In sylefeb/Silice;

· sylefeb opened on Mar 11, 2023

Many boards share a common set of features, yet each board has its own define

discussion

Status: Open.

#246 In sylefeb/Silice;

· sylefeb opened on Mar 5, 2023

pipeline sync

feature

Status: Open.

#241 In sylefeb/Silice;

· sylefeb opened on Feb 12, 2023