Learn VHDL and SystemVerilog
by writing real code.

-- A 4-bit counter: counts up while en is high
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_counter is
  port (
    clk   : in  std_logic;
    rst   : in  std_logic;
    en    : in  std_logic;
    count : out std_logic_vector(3 downto 0)
  );
end entity pulse_counter;
architecture rtl of pulse_counter is
  signal count_r : unsigned(3 downto 0);
begin
  -- One register and one adder: that's the
  -- whole design once it reaches silicon
  process (clk) is
  begin
    if rising_edge(clk) then
      if rst = '1' then
        count_r <= (others => '0');
      elsif en = '1' then
        count_r <= count_r + 1;
      end if;
    end if;
  end process;
  count <= std_logic_vector(count_r);
end architecture rtl;