Zip CPU

@zipcpu

FPGA design engineer and blogger, placing particular emphasis on test and formal verification

Gisselquist Technology, LLC,

zipcpu.com

Joined January 2017

238 Following

8,804 Followers

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Zip CPU
@zipcpu
Oct 4, 2018
Wow, lots of new twitter followers just joined. Welcome! Just to give you an opportunity to get to know me and the ZipCPU blog, here's a bit about me and what you can expect here: zipcpu.com/blog/2018/10/0… Again, welcome!
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Zip CPU
@zipcpu
Oct 24
Perhaps a picture would do a better job explaining what happened ... The good news is that regressions are now passing (again) following a simple fix (S/W change only) to move the sample clock earlier.
Zip CPU
@zipcpu
Oct 23
Today's bug: two simulators (XCelium, Icarus), same logic, one test case passes, one doesn't. Why? It's a race condition. The model sets its data on the same cycle as it gets sampled. One simulator samples the data before it gets set by the model, the other afterwards.
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Zip CPU
@zipcpu
Oct 23
Today's bug: two simulators (XCelium, Icarus), same logic, one test case passes, one doesn't. Why? It's a race condition. The model sets its data on the same cycle as it gets sampled. One simulator samples the data before it gets set by the model, the other afterwards.
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Zip CPU
@zipcpu
Oct 22
Today's bug of the week is a story. It starts with a commercial memory controller (built by yours truly), that passes all of its simulation tests. Reads tested, writes tested, WRAP tested, Exclusive access checked, etc. Many, but not all components were formally verified.
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Zip CPU
@zipcpu
Oct 13
I can't say I've never made this mistake before Note that TFR_WRITE != TFR_TXPARITY ... otherwise this might've worked accidentally ...
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