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Computer Architecture with an Industrial RISC-V Core [RVfpga] (LFD119x)

RISC-V, an open-standard computer architecture, is transforming processor design and software/hardware co-design, including enabling open source hardware implementations. This means that software development can occur alongside hardware development, accelerating the design process. Enroll today to develop your understanding of the RISC-V architecture and its ecosystem and get familiar with the RISC-V cores and system-on-chip.

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Who Is It For
This course is for junior level or higher university computer science, electrical and computer engineers and other technical students as well as others who would like to learn and experiment with RISC-V.
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What You’ll Learn
The course provides hands-on experience with RISC-V computer architecture and teaches how to develop and compile C and RISC-V assembly code for the RVFpga SoC as well as how to use and extend the input/output system of the RVfpga SoC. Additionally, you will learn how to configure the microarchitecture of the VeeR EH1 CoreTM and test its different features using performance counters and industry-standard benchmarks. Finally, the course provides step-by-step instructions on how to execute programs on the Nexys A7 board and simulate programs using: Whisper instruction set simulator (ISS); Verilator-based RVfpga-ViDBo; RVfpga-Pipeline; and RVfpga-Trace.
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What It Prepares You For
Upon completion, learners should be able to use RISC-V to improve security, power consumption and performance of processors and help shape the future of computer architecture.
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Course Outline
Image Welcome to LFD119x!
Image Chapter 1. Installation and Initial Demonstrations
Image Chapter 2. C Programming with the RVfpga SoC
Image Chapter 3. RISC-V Assembly Programming with the RVfpga SoC
Image Chapter 4. RISC-V Function Calls
Image Chapter 5. Mixing C and Assembly Functions in a Program
Image Chapter 6. Introduction to Peripherals and Input/Output
Image Chapter 7. More I/O: 7-Segment Displays
Image Chapter 8. More I/O: Timers
Image Chapter 9. Interrupts
Image Chapter 10. Delving Deeper into the RISC-V VeeR Core
Image Final Exam (verified track only)
Prerequisites
Knowledge prerequisites:

  • Learners should have a fundamental understanding of the following topics: digital logic design, high-level programming (such as C programming), assembly programming, RISC-V instruction set architecture, processor microarchitecture, and memory and input/output systems.

System prerequisites:

  • The software and optional hardware is supported in Linux, and most of it is also supported in Windows and macOS. A Ubuntu 22.04 Virtual Machine is also provided with everything installed on it, so that you can easily use all tools in a Linux environment (independently of the OS that you use in your computer) out-of-the-box. The course may be completed in simulation, so the hardware (the Nexys A7 FPGA board) is optional.
Reviews
Jun 2024
The content was very detailed and well-presented.
Jun 2024
I liked the practical demos on the Nexys A7 board.
Mar 2024
The ability to run the FPGA in several simulators. The provided Ubuntu image with all tools already set up. The wide coverage of the content. Big thanks to the content authors Sara Harris and Daniel Chaver-Martinez.
Mar 2024
The training was very well prepared. This was very important as the complexity in this course is very high. Providing an Ubuntu image with all tools already set up was very appreciated.
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Includes
Image Online, Self Paced
Image 20-40 Hours of Course Material
Image Hands-on Labs & Assignments
Image Discussion Forums
Image 10 Weeks of Free Access to Online Course
Image Optional Paid Certificate of Completion (verified track only)
Experience Level: Advanced
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