Argument LayoutLoop with New FEATUERs and Correctness Patch

[JianmingTONG]

1. Added Energy Efficiency Updates: See following energy efficiency section.
2. Added Bypass Support: Skip the bank conflict analysis for the bypassed dataspace for each memory hierarchy.
3. Distinguish Bank Conflict Analysis into two Pieces: Spatial Analysis (Need to provide the concurrently requested data per cycle); Temporal Analysis: during the processing of the next-level tile, the current-level buffer could provide all requested data.
4. Rename variables following terminology of “mapping parallelism” and “binding parallelism”

• Parallelism at Mapping Step: Let I be an operational iteration space and let f:I→D be a mapping that selects data elements along a particular rank r. Parallelism at mapping step P_{map} is defined as the maximum number ​ of distinct data elements in rank r that can be simultaneously requested by the mapping f during one operational cycle.
• Parallelism at Binding Step (previously “Rank Parallelism”): Let T be an n-dimensional tensor stored in memory, and let r denote one of its ranks (referring to a dimension of the tensor from memory view). Parallelism at binding step P_{bind} is defined as the maximum number of elements along rank r that can be concurrently accessed from a given "buffer" in a single clock cycle.

5. Skip obviously zero bank conflict cases for performance speedup.
6. Support arbitrary number of memory hierarchies including dummy ones used in Eyeriss for better mapping search