cgen,slow_tests: add riscv64 inline asm support, add tests (#26050)

Author: tankf33der

.github/workflows/riscv64_linux_ci.yml

@@ -50,4 +50,5 @@ jobs:
             file ./v
             ls -la ./v
             ./v test vlib/builtin vlib/os vlib/encoding/binary
+            ./v test vlib/v/slow_tests/assembly
             VTEST_ONLY=closure ./v test vlib/v/tests

vlib/v/gen/c/cgen.v

@@ -3293,7 +3293,8 @@ fn (mut g Gen) asm_stmt(stmt ast.AsmStmt) {
 		}
 		// swap destination and operands for att syntax, not for arm64
 		if template.args.len != 0 && !template.is_directive && stmt.arch != .arm64
-			&& stmt.arch != .s390x && stmt.arch != .ppc64le && stmt.arch != .loongarch64 {
+			&& stmt.arch != .s390x && stmt.arch != .ppc64le && stmt.arch != .loongarch64
+			&& stmt.arch != .rv64 {
 			template.args.prepend(template.args.last())
 			template.args.delete(template.args.len - 1)
 		}
@@ -3370,7 +3371,8 @@ fn (mut g Gen) asm_arg(arg ast.AsmArg, stmt ast.AsmStmt) {
 		ast.IntegerLiteral {
 			if stmt.arch == .arm64 {
 				g.write('#${arg.val}')
-			} else if stmt.arch == .s390x || stmt.arch == .ppc64le || stmt.arch == .loongarch64 {
+			} else if stmt.arch == .s390x || stmt.arch == .ppc64le || stmt.arch == .loongarch64
+				|| stmt.arch == .rv64 {
 				g.write('${arg.val}')
 			} else {
 				g.write('\$${arg.val}')
@@ -3387,7 +3389,9 @@ fn (mut g Gen) asm_arg(arg ast.AsmArg, stmt ast.AsmStmt) {
 			g.write('\$${arg.val.str()}')
 		}
 		ast.AsmRegister {
-			if stmt.arch == .loongarch64 {
+			if stmt.arch == .rv64 {
+				g.write('${arg.name}')
+			} else if stmt.arch == .loongarch64 {
 				g.write('$${arg.name}')
 			} else {
 				if !stmt.is_basic {

vlib/v/slow_tests/assembly/asm_test.rv64.v

@@ -0,0 +1,66 @@
+fn test_inline_asm_rv64() {
+	a, mut b := i64(123), i64(0)
+	asm rv64 {
+		// op dst, src
+		mv t0, a
+		mv b, t0
+		; +r (b)
+		; r (a)
+		; t0
+	}
+	assert a == b
+
+	mut c := 0
+	asm rv64 {
+		li c, 5
+		; +r (c)
+	}
+	assert c == 5
+
+	d, e, mut f := 10, 2, 0
+	asm rv64 {
+		mv f, d
+		add f, f, e
+		addi f, f, 5
+		; +r (f)
+		; r (d)
+		  r (e)
+	}
+	assert d == 10
+	assert e == 2
+	assert f == 17
+
+	g, h, mut i := 2.3, 4.8, -3.5
+	asm rv64 {
+		fadd.d i, g, h
+		; =f (i)
+		; f (g)
+		  f (h)
+	}
+	assert g == 2.3
+	assert h == 4.8
+	assert i == 7.1
+
+	n1, n2, mut sum, mut prod := 3, 5, -1, -1
+	asm rv64 {
+		add '%0', '%2', '%3'
+		mul '%1', '%2', '%3'
+		; =&r (sum)
+		  =r (prod)
+		; r (n1)
+		  r (n2)
+	}
+	assert sum == 8
+	assert prod == 15
+
+	l := 5
+	m := &l
+	asm rv64 {
+		li t0, 7
+		sd t0, [m]
+		; ; r (m)
+		; memory
+		  t0
+	}
+	assert l == 7
+}