./wip/OpenSTA, Gate level static timing verifier

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Branch: CURRENT, Version: 2.6.0.1628, Package name: OpenSTA-2.6.0.1628, Maintainer: pkgsrc-users

OpenSTA is a gate level static timing verifier. As a stand-alone
executable it can be used to verify the timing of a design using
standard file formats.

* Verilog netlist
* Liberty library
* SDC timing constraints
* SDF delay annotation
* SPEF parasitics

Master sites:

Version history: (Expand)