How to design a digital-controlled PFC, Part 4
High efficiency is key in applications such as data centers, and new standards codify the now-mandatory requirements.
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The RF-ready GaN-on-silicon with lower parasitic losses
A new technology reduces parasitic channel losses in GaN-on-silicon while boosting linearity and lowering power consumption.
How to design a digital-controlled PFC, Part 4
High efficiency is key in applications such as data centers, and new standards codify the now-mandatory requirements.
MLPerf and the rise of latency-aware LLM benchmarking
Here is a sneak peek at the evolution of the MLPerf benchmark and how generative AI forced a radical shift in AI hardware evaluation.
Memory card interfaces keep pace with the internal bus evolution race: Part 1
Clock speeds get faster. Per-cycle (and per-clock edge) address and data dollops get larger. And protocols get more efficient. But here we’re talking about external, not internal, buses.
