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[RISC-V] Illegal instruction by Clang for FP rounding mode intrinsics #117909
Description
Clang 19 and 20 generate illegal instruction when an implicit FP rounding mode intrinsic used after an Explicit FP rounding mode intrinsic. A test case example:
$ cat 0.c
#include <riscv_vector.h>
#define dataLen 1
float a[dataLen]; float b[dataLen];
int main(){
for (int i = 0; i < dataLen; ++i) { a[i] = 1.0; }
for (int i = 0; i < dataLen; ++i) { b[i] = 0; }
int avl = dataLen;
float* ptr_a = a; float* ptr_b = b;
for (size_t vl; avl > 0; avl -= vl){
vl = __riscv_vsetvl_e32m1(avl);
vfloat32m1_t va = __riscv_vlse32_v_f32m1(ptr_a, 4, vl);
va = __riscv_vfsqrt_v_f32m1_rm( va, __RISCV_FRM_RNE, vl);
va = __riscv_vfredosum_vs_f32m1_f32m1(va, va, vl);
__riscv_vse32_v_f32m1(ptr_b, va, vl);
ptr_a += vl;
ptr_b += vl;
}
return 0;
}
$ /home/compiler/llvm/19.1.4/bin/clang -march=rv64gcv_zvfh -mabi=lp64d -Wno-psabi -static -O1 -save-temps 0.c
$ cat 0.s
...
.LBB0_1: # =>This Inner Loop Header: Depth=1
vsetvli a4, a2, e32, m1, ta, ma
vlse32.v v8, (a0), a3
fsrmi a5, 0
vfsqrt.v v8, v8
fsrmi 7
vfredosum.vs v8, v8, v8
fsrm a5
vse32.v v8, (a1)
slli a5, a4, 2
add a0, a0, a5
subw a2, a2, a4
add a1, a1, a5
bgtz a2, .LBB0_1
...
$ /home/compiler/llvm/19.1.4/bin/clang --version
clang version 19.1.4 (https://github.com/llvm/llvm-project.git aadaa00de76ed0c4987b97450dd638f63a385bed)
Target: riscv64-unknown-unknown-elf
Thread model: posix
InstalledDir: /home/compiler/llvm/19.1.4/bin
The instruction fsrmi 7 is illegal.
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topperc commentedon Nov 28, 2024
This is already fixed on trunk. Possibly by 71b6f6b
topperc commentedon Nov 28, 2024
/cherry-pick 93d7ed542be3ad2c020560adf9ec9f2e4ccacdd7 89658836475d82f0e0a0ace19709921e7a5d3bb5
llvmbot commentedon Nov 28, 2024
Failed to cherry-pick: 93d7ed542be3ad2c020560adf9ec9f2e4ccacdd7
https://github.com/llvm/llvm-project/actions/runs/12060679712
Please manually backport the fix and push it to your github fork. Once this is done, please create a pull request
topperc commentedon Nov 28, 2024
/cherry-pick 71b6f6b 408c84f
llvmbot commentedon Nov 28, 2024
@llvm/issue-subscribers-backend-risc-v
Author: None (rvismith-project)
Details
Clang 19 and 20 generate illegal instruction when an implicit FP rounding mode intrinsic used after an Explicit FP rounding mode intrinsic. A test case example: ``` $ cat 0.c #include <riscv_vector.h> #define dataLen 1 float a[dataLen]; float b[dataLen]; int main(){ for (int i = 0; i < dataLen; ++i) { a[i] = 1.0; } for (int i = 0; i < dataLen; ++i) { b[i] = 0; } int avl = dataLen; float* ptr_a = a; float* ptr_b = b; for (size_t vl; avl > 0; avl -= vl){ vl = __riscv_vsetvl_e32m1(avl); vfloat32m1_t va = __riscv_vlse32_v_f32m1(ptr_a, 4, vl); va = __riscv_vfsqrt_v_f32m1_rm( va, __RISCV_FRM_RNE, vl); va = __riscv_vfredosum_vs_f32m1_f32m1(va, va, vl); __riscv_vse32_v_f32m1(ptr_b, va, vl); ptr_a += vl; ptr_b += vl; } return 0; } $ /home/compiler/llvm/19.1.4/bin/clang -march=rv64gcv_zvfh -mabi=lp64d -Wno-psabi -static -O1 -save-temps 0.c $ cat 0.s ... .LBB0_1: # =>This Inner Loop Header: Depth=1 vsetvli a4, a2, e32, m1, ta, ma vlse32.v v8, (a0), a3 fsrmi a5, 0 vfsqrt.v v8, v8 fsrmi 7 vfredosum.vs v8, v8, v8 fsrm a5 vse32.v v8, (a1) slli a5, a4, 2 add a0, a0, a5 subw a2, a2, a4 add a1, a1, a5 bgtz a2, .LBB0_1 ... $ /home/compiler/llvm/19.1.4/bin/clang --version clang version 19.1.4 (https://github.com/llvm/llvm-project.git aadaa00) Target: riscv64-unknown-unknown-elf Thread model: posix InstalledDir: /home/compiler/llvm/19.1.4/bin ```The instruction
fsrmi 7is illegal.llvmbot commentedon Nov 28, 2024
/pull-request #117948