After completing the programming related to FPGA design, we need to write a tb file for functional verification. Here is a framework: ‘timescale 1ns/1ps module tb_module_name(); /* Input signals of the test module: signal types are defined as reg, ensure bit width consistency, ending with a semicolon */ /* Output signals of the test module: … Read more
Most people have encountered this situation: after putting in a lot of effort to fix the code and test files, you excitedly start running simulations, only to find that everything fails, and you have to spend more effort debugging. This article summarizes two good habits that can improve development efficiency and experience. They are called … Read more
Welcome to leave a message, each message will be selected, and I will reply on the same day. Any errors in the article will also be updated in the reply. #FPGA #UART Transmission #Volatility Generation #Timing Logic The Verilog code is at the bottom of the article. 1. Design File <span>uart_byte_tx</span> Function Analysis This module … Read more
Click to follow the above “Two Monkey Society“ Set as “Top or Star“, and the valuable content will be delivered first. IC Monkey | Two Monkey Society Introduction The previous articles have covered the design part, and this article will analyze the simulation part of the code. This article mainly explains the overall simulation method … Read more
1. What is UART? As one of the three commonly used low-speed buses (UART, SPI, IIC), UART plays an important role in designing various communication interfaces and debugging. UART stands for Universal Asynchronous Receiver/Transmitter, which is mainly used for serial data transmission, and operates in a full-duplex mode. When sending data, it converts parallel data … Read more
