Avoid voltage loss and protect FETs from static energy
Old fashioned p-n junction devices suffered from a voltage drop (0.6V for Si, 0.2V for Ge, if I remember correctly).
FETs and CMOS were the latest highlight back then, and highly prone to be destructed from static electricity ("don't touch with your fingers").
That does not look like a problem nowadays.
How is that achieved?
1 answer
CMOS chips are still susceptible to static discharges today, but less so than they used to be.
The FET gates themselves are still basically the same, and are damaged by over-voltage even for a short time. The difference is that today there are better (or any) static discharge shunt circuits built into ICs.
A static discharge protection circuit can be as simple as reverse diodes to power and ground. In some cases, they can be quite sophisticated, especially when a pin is allowed to be a few volts below ground or above power. A good example of the latter is a "5 V tolerant" pin of a microcontroller that runs from 3.3 V power.
0 comment threads
0 comment threads