Feedback on 48V power control with reverse polarity and opto latch control
I have designed a two-stage power supply and control power circuit. The design allows the entire system to be powered and controlled using a single external push switch (when pressed, it is shorted to ground and when released the line is open) connected to the Opto Power Enable circuit. The same switch both turns ON the main 48 V rail and later allows the MCU (when ON) to sense user input (for example, to wake up, activate Bluetooth). The 48V input is coming from the battery. The 48V first goes through series of bulk caps connected to the Phase driving MOSFETS and then it comes to logic board.
Initial Power-OFF State
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The 48 V input from the battery passes through the slow blow fuse and reverse-polarity MOSFET (Q1) SQ2337ES-T1_BE3 and fuse, but the high-side MOSFET Q7 (FQU12P10) is OFF.
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When Q7 is off, no voltage reaches the 48 V -> 12 V DC DC converter, so all downstream supplies (12 V, 5 V, 3.3 V) are also off.
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Only a few components remain biased — mainly the optocoupler input (U10) and small bias resistors — so standby current is <1 mA.
User Presses the Power Switch
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The LED- is connected to the Switch input which is shorted to ground when switch is pressed and the optocoupler turns on and drives its transistor output low.
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This pulls down the collector of QF2 (2N5551) through R78/R79, turning Q7 ON (QF2 is OFF at this time)allowing 48 V to reach the DC-DC converter TEL15-4811N.
At this point, the 12 V, 5 V, and 3.3 V rails start up, and the MCU becomes powered.
Power Keeper
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As the 3.3 V rail rises, the MCU and the logic circuit (U9/U4) are powered.
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The User will keep the switch pressed until MCU takes control (100ms time approx)
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The latch is maintained from the MCU control logic which turns ON the QF2. The switch can be released, and the 48 V supply stays ON continuously
MCU-Controlled Power-Off (Power Kill)
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In Idle state to save power, the MCU asserts PWR_KILL_SIG_A/B to logic gates (U9 and U4).
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The AND-gate output then drives QF2 base low, turning QF2 OFF.
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With QF2 off, Q7 gate rises to 48 V via pull-ups (R78/R79), and Q7 turns OFF.
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The 48 V line to the DC-DC converters is cut, removing all secondary supplies and fully shutting down the system.
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The standby current returns to microamp levels, leaving only the optocoupler input bias active.
Questions for review
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Is the P-MOSFET-based reverse polarity protection design good?, or should I use two back to back P-MOSFET for reverse current blocking ?
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For surge handling, is SMBJ58A (58V) appropriate for 48V nominal?
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Is the optocoupler latch (LTV-357T) stable and low-leakage, or is there a better MOSFET-based approach?
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Do I need to add a self latch circuit to keep the Q7 turn on even before MCU takes over the control ?
Any suggestions to further reduce standby current and improve overall robustness from ESD, Short Circuit and Overvoltage?
1 answer
immediate comments, going left to right in circuit:
- C61 ... can form undamped LC with input wiring, and thus overshoot to nearly twice Vin on plugin (or more likely some V a bit above Vbr at which TVS and the cap together eat the inrush). If placed right at the input, consider higher V rating?
- D3 5.0SMDJ64A ... max Vbr =~ 79V (not to speak of Vcl). This is vs Q1 Vds_max=80V
- D9 placement no good, will always conduct
- Q1 in general ... how much current is used? Can you tolerate just using a large diode?
- Q7 ... what's the rationale for the inner PMOS being different, and bigger, than the outer one?
- U10/R59 ... are you sure 48V/100k = 480uA (nominal) will turn on the opto reliably enough?
As to how to go about the latching functionality I'm reading from the description? TBH there are probably dedicated IC's for this, depending on the application. That aside, my thought would be to ensure that both the output node "+48V_SW" and the 3.3V node are thoroughly turned off.
Below is an idea for the latching startup/shutdown functionality, without addressing the reverse voltage or transient protection. I am assuming an implicit requirement, to keep the PMOS off until the +48V_SW node has been brought down even lower than the voltage at which the MCU would turn off.
Turn-on: Everything is off until the switch has been pressed. The switch creates a temporary turn-on path for the PMOS gate, which raises the +48V output node. That in turn energizes the 3.3V zener, and from that, the common-base NPN turns on thru the 3.3k resistor, keeping the PMOS on without needing the switch any more. I'd consider a small cap parallel to the 3.3V zener, just for peace of mind vs transients on the 48V node.
Turn-off: Logic signals OFF_A or OFF_B activate the PNP-NPN shutdown-latch, bringing down the 3.3V that came from the zener - down to something in the neighborhood of 1V? At that voltage, the common-base will be off or weak enough that the PMOS should be off. It should be verified that the 3.3V rail is low enough in the latched-shutdown condition, that the MCU cannot turn on.
Or using a flip-flop, with the logic family selected to keep its state down to <1V on the 3.3V rail:
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